Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 myDCM2 : fdiv port map (-- Clock in ports clk_in => i_CLK, -- Clock out ports CLK_out => s_CLK_20M, div =>2 ); myDCM : fdiv port map (-- Clock in ports clk_in => i_CLK, -- Clock out ports CLK_out => s_CLK_5M, div => 25 ); -- --u1:sd_controller -- port map -- ( -- cs => o_MMC_CS, -- mosi => o_MMC_DI, -- miso =>i_MMC_DO, -- sclk => o_MMC_SCK, -- -- rd => rd, -- wr =>wr, -- dm_in => '0', -- data mode, 0 = write continuously, 1 = write single block -- reset =>i_SYS_RESET, -- din =>din, -- dout => dout, -- clk =>CLK_twice -- twice the SPI clk -- ); ---- Inst_PISO_LED: PISO generic map ( g_DataWidth => 16 ) PORT MAP( i_CLK => s_CLK_5M, i_Data => s_LEDs, o_CLK => open, o_Data => o_LEDData, o_Latch => o_LEDLatch ); o_PSCLK <= not s_CLK_5M; ----------------------------------------------------------------------------------- ----------------------------------------------------------------------------------- ----------------------------------------------------------------------------------- -- i_Eth_INT- o_USB_SLOE <='1'; --s_USB_SLOE when s_Interface_Type = c_USB_INTERFACE else '1'; s_USB_PktEND <= '1'; s_USB_IFCLK <= s_CLK_20M; ---------------------------------- s_Data_DIR <= s_W_RD_WRB; s_DATA_Out <= s_W_DATA_Out ; s_W_DATA_In <= s_DATA_In; s_USB_FD_In <= s_DATA_In; ---------------------------------- io_MuxEthUSB(4) <= s_W_ADDR(4); io_MuxEthUSB(9) <= s_W_ADDR(9); io_MuxEthUSB(0) <= s_W_ADDR(0); io_MuxEthUSB(1) <= s_W_ADDR(1) ; io_MuxEthUSB(8) <= s_W_ADDR(8) ; io_MuxEthUSB(7) <= s_W_ADDR(7) ; io_MuxEthUSB(6) <= s_W_ADDR(6) ; io_MuxEthUSB(5) <= s_W_ADDR(5) ; ---------------------------------- Inst_Mux_IOBUF1 : IOBUF generic map ( --DRIVE => 24, IOSTANDARD => "DEFAULT", SLEW => "FAST") port map ( O => s_USB_FLAGA, -- Buffer output IO => io_MuxEthUSB(2), -- Buffer inout port (connect directly to top-level port) I => s_W_ADDR(2), -- Buffer input T => s_Interface_Type -- 3-state enable input, high=input, low=output ); Inst_Mux_IOBUF2 : IOBUF generic map ( --DRIVE => 24, IOSTANDARD => "DEFAULT", SLEW => "FAST") port map ( O => s_USB_FLAGD, -- Buffer output IO => io_MuxEthUSB(3), -- Buffer inout port (connect directly to top-level port) I => s_W_ADDR(3), -- Buffer input T => s_Interface_Type -- 3-state enable input, high=input, low=output ); ---------------------------------- Inst_Data_IOBUF_Generate : for i in 7 downto 0 generate begin Inst_Data_IOBUF : IOBUF generic map ( --DRIVE => 24, IOSTANDARD => "DEFAULT", SLEW => "FAST") port map ( O => s_DATA_In(i), -- Buffer output IO => io_DATA(i), -- Buffer inout port (connect directly to top-level port) I => s_DATA_Out(i), -- Buffer input T => s_Data_DIR -- 3-state enable input, high=input, low=output ); end generate; --o_Eth_RST <= i_SYS_RESET; s_Eth_ReConfig <= i_SYS_RESET; ----------------------------------------------------------------------------------- Wiznet_Config_Process : process(s_CLK_20M) variable odd: std_logic_vector(7 downto 0):=x"00"; variable s_Index_v: integer range 0 to 255:=0; begin if rising_edge(s_CLK_20M) then o_Eth_RST <= '1'; s_WriteTrig <= '0'; case s_Eth_Config_State is when c_Eth_Config_State_Idle => s_Interface_Type <= c_LAN_INTERFACE; s_cnt_Wiznet_Config <= s_cnt_Wiznet_Config + 1; if s_Wiznet_Ini_Reset = '0' then--Reset Cycle Time = 2us ; PLL Lock-in Time = 10ms o_Eth_RST <= '0'; if s_cnt_Wiznet_Config > 20000 then -- 20000 * 50ns = 1ms -- min 2us s_Wiznet_Ini_Reset <= '1'; s_cnt_Wiznet_Config <= 0; --o_Eth_RST <= not o_Eth_RST ;--'0'; end if; elsif s_Wiznet_Init_PLL = '0' then if s_cnt_Wiznet_Config > 300000 then -- 240000 * 50ns = 12ms -- min 10ms s_Wiznet_Init_PLL <= '1'; s_cnt_Wiznet_Config <= 0; end if; else s_Eth_Config_State <= c_Eth_Config_State_Config1; -- s_Index <= 0; end if; when c_Eth_Config_State_Config1 => s_W_ADDR_Des <= c_WIZNET_INIT_ADDR(s_Index); s_W_DATA_Out_Des <= c_WIZNET_INIT_DATA(s_Index); s_WriteTrig <= '1'; s_Index <= s_Index + 1; if s_Index < c_WIZNET_INIT_DATA_LENGTH-1 then s_Eth_Config_State <= c_Eth_Config_State_Config2; else s_Eth_Config_State <= c_Eth_Config_State_End; end if; when c_Eth_Config_State_Config2 => if s_W_DATA_Out_Des_Done = '1' then s_Eth_Config_State <= c_Eth_Config_State_Config1; end if; when c_Eth_Config_State_End => --s_Interface_Type <= c_USB_INTERFACE; if s_Eth_ReConfig = '0' then s_Wiznet_Ini_Reset <= '0'; s_Wiznet_Init_PLL <= '0'; s_Eth_Config_State <= c_Eth_Config_State_Idle; end if; s_Index<=0; s_Eth_Config_State <= c_Eth_INITSOCKET_State; -- WHEN c_Eth_INITSOCKET_State => s_W_ADDR_Des <= c_WIZNET_INIT_SOCKET_ADDR(s_Index); s_W_DATA_Out_Des <= c_WIZNET_INIT_SOCKET_DATA(s_Index); s_WriteTrig <= '1'; -- s_Index <= s_Index + 1; if s_Index < c_WIZNET_INIT_SOCKET_ADDR_LENGTH-1 then s_Eth_Config_State <= c_Eth_INITSOCKET1_State; else s_Eth_Config_State <= c_Eth_INITSOCKET_State_End; end if; s_Index <= s_Index + 1; when c_Eth_INITSOCKET1_State => if s_W_DATA_Out_Des_Done = '1' then s_Eth_Config_State <= c_Eth_INITSOCKET_State; end if; when c_Eth_INITSOCKET_State_End => s_Index<=0; s_W_ADDR_Des <= "10" & x"00"; s_W_DATA_Out_Des <= x"01"; s_WriteTrig <= '1'; s_Eth_Config_State <=c_Eth_delay3_State ;--c_Eth_Start_State; when c_Eth_Start_State => s_W_ADDR_Des <= c_WIZNET_START_ADDR(s_Index); s_W_DATA_Out_Des <= c_WIZNET_START_DATA(s_Index); s_WriteTrig <= '1'; if s_Index < c_WIZNET_START_ADDR_LENGTH-1 then s_Eth_Config_State <= c_Eth_Start_State2; else s_Eth_Config_State <= c_Eth_START_State_End; end if; s_Index <= s_Index + 1; when c_Eth_Start_State2 => if s_W_DATA_Out_Des_Done = '1' then s_Eth_Config_State <= c_Eth_START_State; end if; When c_Eth_START_State_End => s_Index<=0; s_Eth_Config_State <= c_Eth_check1_State; when c_Eth_check1_State=> -- s_W_ADDR_Des <="10"&x"09"; --S0_SSR -- s_ReadTrig <= '1'; -- if s_W_DATA_In_Des_Rdy='1' then -- mode<=s_W_DATA_In_Des; -- s_LEDs<=x"ff" & mode ; -- if mode=x"13" then -- s_Index <=0; -- s_LEDs<=x"00" & mode ; -- s_W_DATA_In_Des<= x"00"; s_Eth_Config_State <=c_Eth_listen_State; -- else -- s_W_ADDR_Des <= c_WIZNET_START_ADDR(3); --CR1 -- s_W_DATA_Out_Des <= x"10"; --close -- s_WriteTrig <= '1'; -- if s_W_DATA_Out_Des_Done = '1' then -- s_Index <=0; -- s_Eth_Config_State <=c_Eth_Start_State; -- end if; -- end if; -- end if; when c_Eth_delay3_State => counter<=counter+1; if (counter<4000) then s_Eth_Config_State <= c_Eth_delay3_State; else counter<=0; s_Eth_Config_State <= c_Eth_Start_State;--c_Eth_listen_State; end if; when c_Eth_listen_State => s_W_ADDR_Des <= c_WIZNET_START_ADDR(3); --cr1 s_W_DATA_Out_Des <= x"02"; s_WriteTrig <= '1'; if s_W_DATA_Out_Des_Done='1' then s_Eth_Config_State <= c_Eth_delay_State; end if; when c_Eth_delay_State => counter<=counter+1; if (counter<4) then s_Eth_Config_State <= c_Eth_delay_State; else s_Eth_Config_State <= c_Eth_check_State; end if; When c_Eth_check_State => -- s_W_ADDR_Des <="10" & x"09"; --S0_SSR -- s_ReadTrig <= '1'; -- if s_W_DATA_In_Des_Rdy='1' then -- listen<=s_W_DATA_In_Des; -- s_LEDs<=x"00" & listen ; -- if listen=x"14" then ---- s_LEDs<=x"ff" & listen ; -- s_Index <=1; s_Eth_Config_State <= c_Eth_establish_State; -- else ---- s_LEDs<= x"000"& conv_std_logic_vector(s_Eth_Config_State,4) ; -- s_W_ADDR_Des <= c_WIZNET_START_ADDR(3); --CR1 -- s_W_DATA_Out_Des <= x"10"; --close -- s_WriteTrig <= '1'; -- if s_W_DATA_Out_Des_Done = '1' then -- s_Index <=0; -- s_Eth_Config_State <=c_Eth_Start_State; -- end if; -- end if; -- end if; when c_Eth_establish_State => -- s_W_ADDR_Des <=c_WIZNET_START_ADDR(4); --S0_SSR -- s_ReadTrig <= '1'; -- if s_W_DATA_In_Des_Rdy='1' then -- establish<=s_W_DATA_In_Des; -- if establish=x"17" then -- s_LEDs<= establish & x"00"; -- s_Index <=0; -- s_Index_v :=0; s_Eth_Config_State <= c_Eth_Receive_Process_State; -- else -- s_LEDs<= x"1111"; ------ s_W_ADDR_Des <= c_WIZNET_START_ADDR(3); --CR1 ------ s_W_DATA_Out_Des <= x"10"; --close ------ s_WriteTrig <= '1'; ------ if s_W_DATA_Out_Des_Done = '1' then ------ s_Index <=0; -- s_Eth_Config_State <=c_Eth_establish_State; -------- end if; -- end if; -- end if; when c_Eth_delay2_State => counter<=counter+1; if (counter<4) then s_Eth_Config_State <= c_Eth_delay2_State; else s_Eth_Config_State <=c_Eth_establish_State;--c_Eth_cheksize_State; end if; when c_Eth_Receive_Process_State => -- s_LEDs<=x"00" & mode; -- s_Index_v:= s_Index_v+1; -- s_W_ADDR_Des <= c_WIZNET_RXPACK_ADDR(1); --S0_RSR -- s_ReadTrig <= '1'; -- s_Index<= s_Index+1; -- if s_W_DATA_In_Des_Rdy='1' then -- if (s_Index_v<c_WIZNET_RX_ADDR_LENGTH) then -- rsr<=s_W_DATA_In_Des; s_Eth_Config_State <=c_Eth_delay4_State; -- else -- s_Index_v:=0; -- s_Eth_Config_State <=c_Eth_Receive_Process_State; -- end if; -- end if; when c_Eth_delay4_State => counter<=counter+1; if (counter<4) then s_Eth_Config_State <= c_Eth_delay4_State; else s_Eth_Config_State <=c_Eth_cheksize_State; end if; when c_Eth_cheksize_State => -- rsr<=s_W_DATA_In_Des; -- s_LEDs<=x"ff"&s_W_DATA_In_Des; -- s_Eth_Config_State <=c_Eth_Receive_Process_State; -- if(rsr/=x"00") then -- s_LEDs<=x"00" & rsr; -- s_W_ADDR_Des <= "10" & x"00"; -- s_W_DATA_Out_Des <= x"01"; -- s_W_DATA_In_Des<=x"00"; -- s_WriteTrig <= '1'; s_Eth_Config_State <=c_Eth_compare2_State; -- else -- -- s_Eth_Config_State <=c_Eth_Receive_Process_State; -- end if; when c_Eth_compare2_State => s_W_ADDR_Des <= "10" & x"31"; s_ReadTrig <= '1'; if s_W_DATA_In_Des_Rdy='1' then data<=s_W_DATA_In_Des; buff(step)<=data; -- s_LEDs<=x"00" & rsr; s_Eth_Config_State <=c_Eth_Receive_Data_State; end if; when c_Eth_Receive_Data_State => s_LEDs<=x"00" & buff(2); step<=step+1; if(step>10) then step<=0; s_Eth_Config_State <= c_Eth_REC_State; else s_Eth_Config_State <=c_Eth_delay5_State; end if; -- s_W_ADDR_Des <= c_WIZNET_START_ADDR(3); --cr1 -- s_W_DATA_Out_Des <= x"40"; -- s_WriteTrig <= '1'; -- if s_W_DATA_Out_Des_Done='1' then -- s_Eth_Config_State <= c_Eth_REC_State; -- end if; when c_Eth_delay5_State => counter<=counter+1; if (counter<4) then s_Eth_Config_State <= c_Eth_delay5_State; else s_Eth_Config_State <= c_Eth_compare2_State; end if; -- when c_Eth_REC_State => -- s_W_ADDR_Des <= c_WIZNET_START_ADDR(3); --cr1 -- s_W_DATA_Out_Des <= x"40"; -- s_WriteTrig <= '1'; -- if s_W_DATA_Out_Des_Done='1' then -- s_Eth_Config_State <= c_Eth_receive_command_State; -- end if; -- when c_Eth_receive_command_State => -- s_LEDs<=x"AAAA" ; -- if s_W_DATA_In_Des_Rdy='1' then -- s_LEDs<=x"AAAA" ;--& data; -- data<=s_W_DATA_In_Des; -- if data=x"00" then -- s_Eth_Config_State <=c_Eth_compare2_State; -- else -- s_LEDs<=x"ff" & data; -- end if; ---- s_LEDs<=x"00AA"; -- end if; -- when others => s_Eth_Config_State <= c_Eth_Config_State_Idle; end case; end if; end process; ----------------------------------------------------------------------------------- WiznetReadWrite_Process : process(s_CLK_20M) begin if rising_edge(s_CLK_20M) then case s_Eth_RW_State is when c_Eth_RW_State_Idle => o_Eth_CS <= '1'; o_Eth_WR <= '1'; o_Eth_RD <= '1'; s_W_DATA_In_Des_Rdy <= '0'; s_W_DATA_Out_Des_Done <= '0'; if s_WriteTrig = '1' then s_W_RD_WRB <= '0'; o_Eth_CS <= '0'; s_W_ADDR <= s_W_ADDR_Des; s_W_DATA_Out <= s_W_DATA_Out_Des; s_Eth_RW_State <= c_Eth_RW_State_W1; elsif s_ReadTrig = '1' then s_W_RD_WRB <= '1'; -- o_Eth_CS <= '0'; s_W_ADDR <= s_W_ADDR_Des; o_Eth_RD <= '0'; o_Eth_CS <= '0'; s_Eth_RW_State <= c_Eth_RW_State_R1; end if; when c_Eth_RW_State_W1 => o_Eth_WR <= '0'; s_W_DATA_Out_Des_Done <= '1'; s_Eth_RW_State <= c_Eth_RW_State_Idle; -- when c_Eth_RW_State_R1_delay => -- s_Eth_RW_State <= c_Eth_RW_State_R1; when c_Eth_RW_State_R1 => s_W_DATA_In_Des <= s_W_DATA_In; s_W_DATA_In_Des_Rdy <= '1'; s_Eth_RW_State <=c_Eth_RW_State_Idle; when others => s_Eth_RW_State <= c_Eth_RW_State_Idle; end case; end if; end process; ------------------------------------------------------------------------------------------ end Behavioral;
Code VHDL - [expand] 1 2 3 4 variable s_Index_v: integer range 0 to 255:=0; begin s_Index <= s_Index + 1; if s_Index < c_WIZNET_INIT_DATA_LENGTH-1 then
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