Problem in designing multiplexer by vhdl

[Sourabh16]

Hello friends
I am having a problem in designing a multiplexer with "n" select inputs ,2^n data inputs and 1 data o/p using behavorial modelling.
can you help me with that

Regards
Sourabh

 

[TrickyDicky]

signal select : integer range 0 to 2**n-1;

type mux_t is array(0 to 2**n-1) of std_logic_vector(7 downto 0);
signal choices : mux_t;


--assuming select lines are std_logic_vector(n-1 downto 0);
select <= to_integer( unsigned( sel_in) );
output <= choices(select);

--mux done