problem in configuring cyclone FPGA

[mohd_ind00]

conf_done never goes high

Hi All,

I am facing problem while configuring cyclone device, i have the below setup which will give a brief picture of board & my setup.

1. I have Altera EP1C6Q240 device and configuration-device EPCS1S18.
2. I am able to program the configuration device successfully.
3. After removing the Byte Blaster-II cable, my target is not configuring i.e not working.

This is the above setup with which i am going ahead. Infact taking care of all the setiings in Quartus II software, i am not able to configure the device.

Can anybudy explain what settings i am missing, so that it can be helpfull to me.

thanks

regards.

 

[davorin]

No..we don't get the picture...

You only mentioned that you connected an EPCS1 to an EP1C6...that's all..
Have you connected the EPCS1/EP1C6 and ByteBlasterII cable like in page 17 of:

https://www.altera.com/literature/hb/cfg/cyc_c51013.pdf


If yes...come back with your detailed software/programming settings...

 

[mohd_ind00]

Hi Davorin,

Thanks for your response.

I am using the same connections as mentioned in the document. And i am using the AS Configuration mode. I am programming through ByteBlaster II cable.

My software settings are as follows,

1. EP1C6Q240i7, PQFP Package with speed grade- Any.
2. Device & Pin Options > General tab > using auto-restart config....
Configuration > AS scheme, EPCS1 device, Compress..
3. Unused Pins > Inputs as Tri-stated
4. Error Detection CRC > Enabled Error Detection CRC & Divide error check freq by 1.

5.Compilation Process >> using Smart Comp.... + preseve fewer node....

I am not using the INIT_DONE pin.

All other Settings are default.

Pl see if these are correct. Waiting for ur uggestion.

regards

 

[davorin]

If you download your design via JTAG...does it work then?

You know that you can also program the EPCS through JTAG (o;

 

[mohd_ind00]

Hi Davorin,

I did not try with JTAG, b'cos my hardware doesn't support it. Did u see the sofware settings and are they correct?

pl reply
regards

 

[davorin]

Only difference is that I don't use CRC checking...the rest looks fine...


How do you know your design works if you don't have JTAG?
Do you see CONF_DONE going high then?

 

[mohd_ind00]

Hi,

CONF_DONE is not going high and nSTATUS is also low every time.

Is it necessary to use CRC, and if error occur will FPGA starts configurtion again, and how should i come to know that error is occred.

One more thing is that, is it to use 'auto usercode' in device and pin options' general tab.

thanks

regards

 

[my_garden]

Hi mohd_ind00
Maybe you can check the power ciruit for your design. When cyclon in configurtion status, it will takes about 1A current.

 

[mohd_ind00]

Re: problem in configuring cyclone FPGA- Solved

Hi Mr Davorin & all

I solved the problem configuring cyclone FPGA, the thing is i was not getting supply to the PLL ckt.

Now it is configured well after correcting the problem.

Thanks for all who have replied and helped me a lot.

thanks,

regards

 

[stevepre]

Hi mohd_ind00,

Could you detail exactly what was the problem before?

I am getting the same problem, except that I am using Stratix.

I also tried using JTAG to program Stratix directly, and get the error message saying CONF_DONE didn't go high.

When using EC16->stratix, the CONF_DONE never goes high either.

Please help.....anybody?

Thanks