Problem in Behavioral simulation of CARRY4 primitive

[msdarvishi]

Hello everyone,

I configured a delay line using CARRY4 primitive. I use ISE 14.7 amd VIrtex-5 (XC5VLX50T) device.
There is a question regarding the functionality of the CARRY4 primitive that made me confused that I would like to share it with you to get some hints. You know, the CARRY4 includes 4 carry logics and the output of each must have a certain latency compared to the previous output. I do not know why when I do the post place&route simulation, I see thise latency between each 4 bits of the CARRY4, but as you see in the attached figure, in the behavioral synthesis, all 4 bits (o[0] to o[3]) are changing simultaneously that seems weird compared to the theory behind the CARRY4 functionality ! Could you please guide me about it? I am not interested to perform post place&route simulation since it connects the output bits to the IOBs that the effect of IOs and routing delays will be included in the results.

Thanks and Regards,

 

[TrickyDicky]

Behavioural simulation has no delays. Post place and route sims will have delay.
If you are relying on delays in your system, then you are designing it wrong. You should have everything synchronous so you do not care about delays. As long as your functional simulation is correct and the design meets the timing requirements, internal delays are irrelavent.