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Problem Exporting Verilog file with SEULTRA

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miyone

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Hi, this is my first time posting.

I've got a problem exporting verilog files with Silicon Ensemble. Here is the error message i'm getting.

Code:
22:59:50 * pbohvo  : Reading verilog library files...
** SE-USER-61  ERROR **
22:59:50 * pbohvo  :  While getting cells from std: Library not defined
** SE-USER-61  ERROR **
22:59:50 * pbohvo  :  Unexpected (pbohvo) failure.
22:59:50 * OUTPUT VERILOG CPU 13 :  Failed exporting verilog

Not sure if this has anything to do with synthesis. I use RC Encounter for the synthesis, which is apparently new to me. I didn't get the same problem when i was using Ambit Buildgates before.

Thanks a lot for any help.
 

Atre

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Hi,

Did you compile the library standard cells into your design library?
Also, did you defined also these variables: VerilogLib and DesignLib?

I hope this might help you!

Best regards!
 

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