Problem coding FlipFlop in VHDL

[AMCC]

en_aq

Dear All,
I'm using the following code for creating a FF with synchronous reset and enable:

Run_Condition: PROCESS (aq_clk, en_aq, start, run)
BEGIN
if (aq_clk'event and aq_clk = '1') then
if (en_aq = '0') then
run <= '0';
elsif (start = '1') then
run <= en_aq;
end if;
end if;
END PROCESS Run_Condition;

Initial value of en_aq = '0'. start is a '1' single aq_clk period pulse.
I cannot find any problem in this coding BUT in my simulation a very strange effect happens:
I have an Undefined run between rising(en_aq) and start pulse.
Am I missing something?

Thank you very much for your help.
Best Regards
AMCC

 

[Iouri]

process(aq_clk, en_aq, start)
variable temp: std_logic_vector(1 downto 0);
begin
temp := en_aq & start;
if (aq_clk = '1' and aq_clk'event) then
case (temp ) is

when "00" | "01" =>
run <= '0';
when "11" =>
run <= en_aq;
when others => null;
end case;
end if;
end process;

 

[tkbits]

Or set an initial value:

signal run: std_logic := '0';

 

[salma ali bakr]

exactly like said above, you can set an initial value for "run" before the if statements, or make a case for the missing conditions not covered by your code...or you can simply add an "else" condition before the "end if" to cover the missing conditions (same as adding case)

 

[master_picengineer]

Hi all,
But in synthesis this initial values are not taken into account. How to resolve this problem when device initialization is needed.

 

[AMCC]

Dear all,

Thank you for your comments, but I think that the problem is not the initial value.
'run' WILL start '0' one way or another (either by default initialization or by the fact that en_aq is '0' initially (and this one is properly initialized).
I wonder if there is any difference between using:

if
elsif
endif

OR

if
else if
end if

Is it possible that the synthesizer can have different views of the code?

Thnak you very much for your attention.

Best Regards

AMCC

 

[salma ali bakr]

first of all there's no endif
it's only end if in vhdl

if you say elsif...then it's just the continuation of the if statement before the last else- you can just have if and elsif..or if and else...depends on your design behavior....

but if it's else if...then there's nested if else statements...and that's different in synthesis of course

i guess your problem lies in the if else statements...try to write them properly according to the behavior of the ff you want to have...so my advice add a final else with the conditions that drop out from the first two conditions of run and start

 

[AMCC]

Dear Salma,
Off course "end if" ... my "writing" mistake .

A related question as raised in my head:
What is the difference during for a synthesizer when coding a Flip-Flop with synchronous enable and reset of the two descriptions below?

Description1:

if(clk'event and clk = '1') then
if (reset = '1') then
out <= '0';
elsif( enable = '1') then
out <= input;
end if;
end if;

Description 2:

if(clk'event and clk = '1') then
if (reset = '1') then
out <= '0';
else
if( enable = '1') then
out <= input;
end if;
end if;
end if;

What is the most "recommendable" and why? (Note: I typically use the Description 1, but the present topic is one of the cases where it seems no to behave as I desire).


Thank you once again.
AMCC

 

[salma ali bakr]

of course the exact implementation of the code depends upon the synthesis tool used and the target architecture of the device....

but generally speaking:
if (without else) infers a latch (avoid this)
if else implies a mux
if else if or if elsif ...imply priority coded logic...with different levels according to the statements written...just imagine as if you have here a mux with a simple input at one pin (the code after the if) and a whole bunch of other logic as the other input (the code after the else if or elsif...etc) that's making another level with muxes...etc

 

[suru]

REFER VHDL BY BHASKER BOOK. EXAMPLES ARE GIVEN.

 

[rajank]

In this program if 'run' mode is out(output port)
then u not put into the process() sensitivity list

or if run is variable then you use variable assignment statement for assiging the value.
like
run := en_aq;

 

[Iouri]

guys it works only in verilog

if cond 1 then statement 1
if cond 2 then statement2

in will build priority encoder

in VHDL thinks are little different

what should happen if cond1 and cond both true, this has to be describe or cond1 and cond2 false.

Regards,