problem about synopsys synthesis

[Rachel]

I write verilog code as below :
always @(posedge clock or posedge rst)
if (rst)
reg1 <= 1'b0 ;
else
reg1 <= 1'b1 ;

Synopsys will synthesis this register with its input connected to VCC , I change some setting in .synopsys_setup ,and let it put a cell between system VCC with its input. The problem is I wish every register's input ( described like before) don't be connected to VCC directly and synopsys can put a cell between it and VCC. I hope one cell to one register , but synopsys will connect all the inputs and only put one cell between them and VCC . The cell is from a library provided by fab , I can't change its fanout . Can I disovle it by setting synthesis constraint ? Can anyone help me ?

 

[cdic]

synthesis it first, then wrote a script to change it. either in DC or directly modify the netlist. piece of a cake.

 

[Rachel]

synthesis it first, then wrote a script to change it. either in DC or directly modify the netlist. piece of a cake.

Do you mean I can change the schematic result by DC command ? Can you give me an example ? Thanks a lot!

 

[cdic]

Cells Create a cell create_cell
Delete a cell remove_cell
Nets Create a net create_net
Connect a net connect_net
Disconnect a net disconnect_net
Delete a net remove_net
Ports Create a port create_port
Delete a port remove_port
Buses Create a bus create_bus
Delete a bus remove_bus

 

[rakko]

Rachel,
how about attach your cell to vcc / ground and assign the other end of this cell to your register inside your always block.

example:

cell (.Z(wire1), .A(VCC));

always .....
if (rst)
reg1 <= 1'b0;
else
reg1 <= wire1;

 

[rakko]

deleted

 

[maniasonic]

you must don't have a cell that always out put a logic "1" in your cell library.

 

[honey]

inside your always block.

example:

cell (.Z(wire1), .A(VCC));

always .....
if (rst)
reg1 <= 1'b0;
else
reg1 <= wire1;