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problem about SC integrator clock frequency

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tranhuuthong

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Dear All,

I am doing my project about Delta sigma Moduration.
I designed SC integrator (see in picture) the requirement for input is 8KHz, but for
bitstream output is about 10MHz.
Please see the wavwform of integrator. does it have problem?

I am worrying clock supply for Switch. because output need feedback for summing, integrator, so I think integrator has to work above 10MHz.
So, Switch clock > 50MHz?

How to make a clock generator at this frequency?

the relationship between clock of Switch (in integrator) and sampling frequency. Are they same? and the clock of FlipFlop D?

does it have a relationship between output bitstream and oversampling rario?

please help me.
 

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    integrator waveform.png
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    integrator.png
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Braski

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I am not sure about your problem.
But the output bitrate should be defined by your oversampling ratio i think. Then, your clock will be given by this frequency.

I would also like to add that a SC also performs sample and hold by itself. So the switch frequency is the SH freq.
 

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