Problem about Inverting signals inside FPGA.

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EDA_hg81

inverting fpga

My situation is as following:
Have to use Virtex E to drive a sensor with 5V TTL logic.
I used NC7ST04 inverter as a level shifter.
https://images.elektroda.net/66_1226541807.jpg
Inside FPGA I wrote code as:
Code:
Signal_out <= not ( signal );
Based on above way, after two inverting the signal is going to be changed to 5V TTL with the same rising and falling edges as inside LVTTL logic.
But the problem is the signal output from FPGA is totally wrong, the voltage is inverted but with a -3.3V offset as in the figure 2th.

https://images.elektroda.net/51_1226541772.jpg

I used the same ground reference measure those two signals.

What is the problem?

yego

Full Member level 3
Pretty odd indeed.
How about checking your .ucf file if the output has been properly defined with a suitable standard ?

EDA_hg81

Points: 2

EDA_hg81

When I switched the proram, I didn't change the probe.

It is so confused.

EDA_hg81

I tried use the component INV.

the same result.

Member level 3
Check your channel 1 setting (on the scope). I believe you have coupling set to AC instead of DC.

EDA_hg81

Points: 2

Siniša

Full Member level 6
Yeah, It's likely AC coupling on his scope.

EDA_hg81

Points: 2

EDA_hg81

yes.

you are so right.

my setting was AC coupling.

Thank you so much.

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