Problem about generic .Can anybody help me? plz

[azwaa]

Hi guys !

I have a big problem with my code about generic

question : How is that the program will be generic ?!

Can you help me plz

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity correla is
generic  (
            longueur  : natural :=8 );
port (
         clk : in    std_logic ;
         rst : in    std_logic  ;
         data: in    std_logic_vector(11 downto 0)  ;
          --code: in    std_logic_vector(15 downto 0 )  ;--for 4 bits
         code: in    std_logic_vector((4*longueur)-1 downto 0 )  ;---for generic
       
            --Q   :out    std_logic_vector(17 downto 0) )  ;--for 4 bits
         Q   :out   std_logic_vector((4*longueur)+1 downto 0)) ; ---for generic
end entity ;
architecture arch of correla  is
       --type RAM is array (0 to 3) of std_logic_vector(3 downto 0) ; --for 4 bits
       type RAM is array (0 to 3) of std_logic_vector(longueur-1 downto 0) ;---for generic
     
       --type ram16 is array (0 to 3) of signed(15 downto 0) ;--for 4 bits
       type ram16 is array (0 to 3) of signed((4*longueur)-1 downto 0) ;---for generic
       --type Rom is array (0 to 3) of signed(11 downto 0) ;--for 4 bits
       type Rom is array (0 to 3) of signed((3*longueur)-1 downto 0) ;---for generic
        signal voie :Rom ;
        signal CD    : RAM;
       
        signal temp: ram16;
     
     
       -- signal sum0   :signed (16 downto 0) ;
         signal sum0   :signed (4*longueur  downto 0) ;---for generic
        --signal sum1   :signed (16 downto 0) ;--for 4 bits
        signal sum1   :signed (4*longueur downto 0) ;---for generic
        --signal AB     :signed (17 downto 0) ;--for 4 bits
        signal AB     :signed ((4*longueur)+1 downto 0) ;---for generic
       
begin
   
                               
                           
    --CD(0) <= code(15 downto 12);--for 4 bits
    --CD(1) <= code(11 downto 8);--for 4 bits
    ---CD(2) <= code(7 downto 4);--for 4 bits
    --CD(3) <= code(3 downto 0); --for 4 bits
   
     AY:for j in 0 to 3 generate
           CD(j)<=(code((longueur*j+(longueur-1)) downto (longueur*j)));---for generic
      end generate AY ;
   
   
     
     etalement:process(clk,rst)
         
        begin
                  if(rst='1') then
                     Q  <=(others=>'0');
                   
                     F:for k in 0 to longueur-1 loop ---for generic
                          temp(k)<=x"0000";
                       end loop ;
                     --temp(0)<=x"0000";--for 4 bits
                     --temp(1)<=x"0000";--for 4 bits
                     --temp(2)<=x"0000";--for 4 bits
                     --temp(3)<=x"0000";--for 4 bits
                   else
                        if(clk'event and clk ='1') then
                              voie(0)<=signed(data) ;
                             
                              B:for L in 1 to 3 loop
                                 voie(L)<=voie(l-1);---for generic
                               end loop ;
                             
                              --voie(1)<=voie(0);--for 4 bits
                              --voie(2)<=voie(1);--for 4 bits
                              --voie(3)<=voie(2); --for 4 bits
                           
                                   
                                      for i in 0 to 3 loop
                                      --for i in 0 to longueur-1 loop
                                        temp(i) <= voie(i)*signed(CD(i));
                                      end loop ;
                                     
                                       --sum0<= resize(temp(0),17)+temp(1) ;--for 4 bits
                                       sum0<= resize(temp(0),(4*longueur)+1)+temp(1) ;---for generic
                                       --sum1<= resize(temp(2),17)+temp(3) ;--for 4 bits
                                      sum1<= resize(temp(2),(4*longueur)+1)+temp(3) ;---for generic
                               
                                        -- AB<=resize(sum0,18)+sum1 ;--for 4 bits
                                         AB<=resize(sum0,(4*longueur)+2)+sum1 ;---for generic
                                       
                                         Q<=std_logic_vector(AB) ;
                                                 
                                 
                             end if ;
                     end if ; 
                                   
                       
                     
            end process ;
end architecture ;

Thank you in advance for your reponse

 

[TrickyDicky]

what exactly is the question? when you instantiate the correla entity, you can set the longueuer generic.

 

[azwaa]

Yes I'm agree with you but

My question is : What I'm should to make for the program work for " langueur"=8,16..

My idea is :https://obrazki.elektroda.pl/2090831700_1402041137.png

Thank you in advance for your reponse

 

[FvM]

I hope you have solved your previous thread. The new thread reminds me to a quote from Douglas Adams Life, the Universe, and Everything:

if it happened, it seems that the Question and the Answer would just cancel each other out and take the Universe with them, which would then be replaced by something even more bizarrely inexplicable.

 

[azwaa]

Error : https://obrazki.elektroda.pl/7049262700_1402044435.png

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F:for k in 0 to longueur-1 loop 
                         temp(k)<=x"0000";----?!
                       end loop ;

 

[FvM]

Yes, the expression lengths doesn't match, as clearly indicated in the error message.

I'm not sure if you pursue a plan? If so, you would change all code locations to generic signal length. In the present place, you can e.g. write (others => '0') as a zero vector of unspecific length.

 

[azwaa]

This is my code :

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;


entity correla is

generic  (
            longueur  : natural :=8 );


port (
         clk : in    std_logic ;
         rst : in    std_logic  ;
         data: in    std_logic_vector(11 downto 0)  ; 

         --code: in    std_logic_vector(15 downto 0 )  ;
         code: in    std_logic_vector((4*longueur)-1 downto 0 )  ;
        
            --Q   :out    std_logic_vector(17 downto 0) )  ;
         Q   :out   std_logic_vector((4*longueur)+1 downto 0)) ;
end entity ;

architecture arch of correla  is 
       --type RAM is array (0 to 3) of std_logic_vector(3 downto 0) ;
       type RAM is array (0 to 3) of std_logic_vector(longueur-1 downto 0) ;
       
       --type ram16 is array (0 to 3) of signed(15 downto 0) ;
       type ram16 is array (0 to 3) of signed((4*longueur)-1 downto 0) ;
       --type Rom is array (0 to 3) of signed(11 downto 0) ;
       type Rom is array (0 to 3) of signed((3*longueur)-1 downto 0) ;

        signal voie :Rom ;
        signal CD    : RAM;
        --signal CD1: std_logic_vector(3 downto 0);
        --signal temp  : std_logic_vector(15 downto 0);
        signal temp: ram16;
       --signal temp1  : std_logic_vector(15 downto 0);
       
        --signal idata :std_logic_vector(15 downto 0) ;
        
       
       -- signal sum0   :signed (16 downto 0) ;
         signal sum0   :signed (4*longueur  downto 0) ;
        --signal sum1   :signed (16 downto 0) ;
        signal sum1   :signed (4*longueur downto 0) ;
        --signal AB     :signed (17 downto 0) ;
        signal AB     :signed ((4*longueur)+1 downto 0) ;

        
begin
     
                                
                            
    --CD(0) <= code(15 downto 12);
    --CD(1) <= code(11 downto 8);
    ---CD(2) <= code(7 downto 4);
    --CD(3) <= code(3 downto 0); 
    
     --AY:for j in 0 to 3 generate 
     
         AY:for j in 0 to 3 generate 
           
           CD(j)<=code((longueur*j)+(longueur-1) downto (longueur*j));
           --CD(longueur-1-j)<=(code((longueur*j+(longueur-1)) downto (longueur*j)));
      end generate AY ;
    
    
       
     etalement:process(clk,rst)
           
        begin 
                  if(rst='1') then 
                     Q  <=(others=>'0');
                     
                    F:for k in 0 to longueur-1 loop 
                         temp(k)<=(others=>'0');----?!
                       end loop ;
                    -- temp(0)<=x"0000";
                     --temp(1)<=x"0000";
                     --temp(2)<=x"0000";
                     --temp(3)<=x"0000";

                   else 
                        if(clk'event and clk ='1') then 
                              voie(0)<=signed(data) ;
                              
                              B:for L in 1 to 3 loop
                              -- B:for L in 0 to longueur-1 loop 
                                 voie(L)<=voie(L-1);
                               end loop ;
                               
                              --voie(1)<=voie(0);
                              --voie(2)<=voie(1);
                              --voie(3)<=voie(2); 
                            
                                     
                                     for i in 0 to 3 loop 
                                     -- for i in 0 to longueur-1 loop 
                                        temp(i) <= voie(i)*signed(CD(i));
                                      end loop ;
                                      
                                       --sum0<= resize(temp(0),17)+temp(1) ;
                                       sum0<= resize(temp(0),(4*longueur)+1)+temp(1) ;
                                       --sum1<= resize(temp(2),17)+temp(3) ;
                                      sum1<= resize(temp(2),(4*longueur)+1)+temp(3) ;
                                
                                        -- AB<=resize(sum0,18)+sum1 ;
                                         AB<=resize(sum0,(4*longueur)+2)+sum1 ;
                                         
                                         Q<=std_logic_vector(AB) ;
                                                  
                                  
                             end if ;
                     end if ;  
                                     
                        
                       
            end process ;
 end architecture

Thank you for your reponse

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Error : Error (10384): VHDL assignment error at correla.vhd(78): index 4 is outside the range (0 to 3) of object "temp"

F:for k in 0 to longueur-1 loop 
                         temp(k)<=(others=>'0');----?!
                       end loop ;

 

[TrickyDicky]

temp is only decalred 0 to 3, hence you cannot access location 4

 

[azwaa]

problem is

 type ram16 is array (0 to 3) of signed((4*longueur)-1 downto 0) ;
                          signal temp: ram16;
                      F:for k in 0 to longueur-1 loop 
                         temp(k)<=(others=>'0');----?!
                       end loop ;

if we have length =4 ==>temp=16
length=8 =>temp=20
length=12 =>temp=24

I should have an relation between temp and length

can you help me plz !!

 

[TrickyDicky]

you have only changed the word length, not the length of the array.

 

[azwaa]

Yes ; can you help me plz .?

 

[TrickyDicky]

I am trying, but it seems you need to be hand held through every compilation error. Here is the clue:

type ram16 is array (0 to 3)

 

[azwaa]

So , I have a big problem !! :sad:

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Can anybody help me :!:

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Can anybody help me :!:

 

[TrickyDicky]

I have told you, you need to make the temp array based on the generic, or change what you are indexing inside the loop.

 

[azwaa]

Hi !



Thank you

 

[Tetik]

From your table, find the relationship between length and the width of temp. I'm sure you're able to find it easily. If you still don't find it, get a dozen of doughnuts box and I'm sure the answer will come.

Gook luck