HF probes tend to be good only for 50-ohm systems. A FET
probe may be better but is not likely good enough.
My test chip strategy tends to be difference based or ring
oscillator based. A good high stage count (prime number)
RO can get you to very good "core gate" delays provided
that you give the RO good local decoupling and make the
output not kick the local rails unduly (like, use a LVDS
output buffer, or resistor-limit a CMOS buffer (maybe even
make the limiter a divider that impedance-matches to
50 ohm cabling, through a bias-T).
Make RO variants that have different wire and fanout loads
(per-stage and identical) and you can readily get to delay
numbers by frequency and N, across supply / temp / load.
Process of course takes more money and/or interaction
with the fab.
Now if you're intent on probing a single naked core-sized
logic gate, I have no encouragement for you there.