probably simple mixed signal spice question.

[kudjung]

74ac spice

Hello All

I'm a newbie to spice. this probably be a simple question. But I don't know why I was getting this. I try to to simulate the simple mixed signal in spice. I put a 100K ohm resistor at the output of a not gate(74F04), I got 3.5 volt(why not 5) as logic high. Why? What I did wrong? I try changing the not gate supply but it also didn't work. I 've attached the picture of the schematic that I use for simulation.

TIA.

 

[EcraZ]

digifpwr

Spice uses a set up library and device models for simulating. you probably have used a digital model. The power in digital devices is specified by a statement in the netlist or in the device properties and not by the voltage souce connected externally. Check out with the manual of the tool u are usin or look into the way the device property specifies the power and then correct it to 5v from 3.5 volts and then u will get it right.

It will be something like $G_DPWR and $G_DGND. also the input and output at the gate is determined by the IO model. so check this too.

 

[flatulent]

hspice for simple gates

Another possible problem is that the program is giving you the worst case high level for the logic family. Try changing to a 74AC type gate family and see if the level is 5 V.

 

[kudjung]

$g_dpwr pspice

Thank you very much for the answer. It was very helpful. The only way I can get the logic HI to be to 5Volts is by changing the gate to the 74AC series. It seem that the software was giving me a worst case high level as pointed out by Flatulent. I've cut and paste the netlist below. This circuit was simulating in Cadedence Pspice(Microsim). Is there anyway I can do the simulation with the VOH(MAX),5V?

Thanks again,



** Analysis setup **
.tran 20ns 1000ns
.OPTIONS DIGINITSTATE=1
.OPTIONS DIGIOLVL=1
.OPTIONS DIGMNTYMX=2
.OP
.LIB "D:\MSim_8\Projects\TEST\Schematic4.lib"


* From [PSPICE NETLIST] section of d:\Cadence\PSD_14.2\tools\PSpice\PSpice.ini:
.lib "nom.lib"

.INC "Schematic4.net"



**** INCLUDING Schematic4.net ****
* Schematics Netlist *



X_U7A $D_LO $N_0002 $G_DPWR $G_DGND 74LS04 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
R_R2 $G_DGND $N_0002 10k

**** RESUMING Schematic4.cir ****
.PROBE V(*) I(*) W(*) D(*) NOISE(*)


.END


**** Generated AtoD and DtoA Interfaces ****

*
* Analog/Digital interface for node $N_0002
*
* Moving X_U7A.U1:OUT1 from analog node $N_0002 to new digital node $N_0002$DtoA
X$$N_0002_DtoA1
+ $N_0002$DtoA
+ $N_0002
+ $G_DPWR
+ $G_DGND
+ DtoA_LS
+ PARAMS: DRVH= 108 DRVL= 157 CAPACITANCE= 0
*
* Analog/Digital interface power supply subcircuits
*
X$DIGIFPWR 0 DIGIFPWR


**** 02/21/03 12:02:31 ******** PSpice 9.2.3 (Jan 2002) ******* ID# 1111111111
* D:\MSim_8\Projects\TEST\Schematic4.sch


**** Digital Input MODEL PARAMETERS


******************************************************************************




DIN74LS
S0NAME 0
S0TSW 5.000000E-09
S0RLO 1
S0RHI 100.000000E+03
S1NAME 1
S1TSW 4.500000E-09
S1RLO 100.000000E+03
S1RHI 1
S2NAME X
S2TSW 4.500000E-09
S2RLO 30.9
S2RHI 100
S3NAME R
S3TSW 4.500000E-09
S3RLO 30.9
S3RHI 100
S4NAME F
S4TSW 4.500000E-09
S4RLO 30.9
S4RHI 100
S5NAME Z
S5TSW 4.500000E-09
S5RLO 200.000000E+03
S5RHI 200.000000E+03


**** 02/21/03 12:02:31 ******** PSpice 9.2.3 (Jan 2002) ******* ID# 1111111111
* D:\MSim_8\Projects\TEST\Schematic4.sch


**** Digital Gate MODEL PARAMETERS


******************************************************************************




D_LS04
TPLHMN 3.600000E-09
TPLHTY 9.000000E-09
TPLHMX 15.000000E-09
TPHLMN 4.000000E-09
TPHLTY 10.000000E-09
TPHLMX 15.000000E-09


**** 02/21/03 12:02:31 ******** PSpice 9.2.3 (Jan 2002) ******* ID# 1111111111
* D:\MSim_8\Projects\TEST\Schematic4.sch


**** Digital IO MODEL PARAMETERS


******************************************************************************




IO_LS
DRVL 157
DRVH 108
AtoD1 AtoD_LS
AtoD2 AtoD_LS_NX
AtoD3 AtoD_LS
AtoD4 AtoD_LS_NX
DtoA1 DtoA_LS
DtoA2 DtoA_LS
DtoA3 DtoA_LS
DtoA4 DtoA_LS
TSWHL1 2.724000E-09
TSWHL2 2.724000E-09
TSWHL3 2.724000E-09
TSWHL4 2.724000E-09
TSWLH1 2.104000E-09
TSWLH2 2.104000E-09
TSWLH3 2.104000E-09
TSWLH4 2.104000E-09
TPWRT 100.000000E+03


**** 02/21/03 12:02:31 ******** PSpice 9.2.3 (Jan 2002) ******* ID# 1111111111
* D:\MSim_8\Projects\TEST\Schematic4.sch


**** SMALL SIGNAL BIAS SOLUTION TEMPERATURE = 27.000 DEG C


******************************************************************************



NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE


($G_DGND) 0.0000 ($G_DPWR) 5.0000

($N_0002) 3.4421 (X$$N_0002_DtoA1.DGND_OL) .1014

(X$$N_0002_DtoA1.DPWR_OH) 3.4424



DGTL NODE : STATE DGTL NODE : STATE DGTL NODE : STATE DGTL NODE : STATE


($N_0002$DtoA) : 1 ( $D_LO) : 0




VOLTAGE SOURCE CURRENTS
NAME CURRENT

X$DIGIFPWR.VDPWR -3.826E-04
X$DIGIFPWR.VDGND -5.000E-06

TOTAL POWER DISSIPATION 1.91E-03 WATTS


**** 02/21/03 12:02:31 ******** PSpice 9.2.3 (Jan 2002) ******* ID# 1111111111
* D:\MSim_8\Projects\TEST\Schematic4.sch


**** OPERATING POINT INFORMATION TEMPERATURE = 27.000 DEG C


******************************************************************************






**** VOLTAGE-CONTROLLED CURRENT SOURCES


NAME X$$N_0002_DtoA1.G_OH X$$N_0002_DtoA1.G_OL
I-SOURCE 3.776E-04 3.341E-05 
**** 02/21/03 12:02:31 ******** PSpice 9.2.3 (Jan 2002) ******* ID# 1111111111
* D:\MSim_8\Projects\TEST\Schematic4.sch


**** INITIAL TRANSIENT SOLUTION TEMPERATURE = 27.000 DEG C


******************************************************************************



NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE NODE VOLTAGE


($G_DGND) 0.0000 ($G_DPWR) 5.0000

($N_0002) 3.4421 (X$$N_0002_DtoA1.DGND_OL) .1014

(X$$N_0002_DtoA1.DPWR_OH) 3.4424



DGTL NODE : STATE DGTL NODE : STATE DGTL NODE : STATE DGTL NODE : STATE


($N_0002$DtoA) : 1 ( $D_LO) : 0




VOLTAGE SOURCE CURRENTS
NAME CURRENT

X$DIGIFPWR.VDPWR -3.826E-04
X$DIGIFPWR.VDGND -5.000E-06

TOTAL POWER DISSIPATION 1.91E-03 WATTS