Proasic ram models for verilog

[praveen_baba]

hi friends
i am tring to simulate the can code which i downloaded form the opencores initially how the functionality works in simulation.After that i will improve the code.but i am getting one problem,there is missing verilog code for the Proasic ram actel model 64X1 and 64X4 verilog models

i am already tried in actel site also unable to get the these models.can any one help me how to get this models.


Thanks in adv