Priority arbiter concept using AXI4-Lite signals

[dpaul]

Hi,

I want to design a priority based arbiter to be used in an AXI4 N-to-M Interconnect (shared access Mode) which as multiple AXI4-Lite masters and slaves.
In this env. one master will have the highest priority and this master will also enjoy default-grant.

My idea is to make use of the arvalid and awvalid output signals from each master to generate the grant signals in the arbiter logic block.

Are the above mentioned signals sufficient to serve this purpose?

 

[ads-ee]

I am not be an expert with AXI but I can't think if any reason that wouldn't work. A master will be held until it recieves a respones.