primetime check different clock

[megastar007]

Clock domain Crossing

Can any one tell different methods for transffering CONTINOUS data(not single bit,say byte or word) between 2 clk domains (other than Async FIFO).

 

[BlueSky68]

Re: Clock domain Crossing

One should avoid to pass a lot of data acrossing the clock domains. If you have to, FIFO might be the best scheme to use. However, I personally like to use control signal to gate the very wide data bus for clock domain crossing. This way, it is very clean and easily to do STA.

Also, cross from fast to slow, or slow to fast manifesst two different kind of chanllenges as well..


Hope it helps.

 

[amitgvlsijune06]

Re: Clock domain Crossing

In a circuit where an asynchronous signal has to be synchronised with the clk,the MTBF comes into picture.
MTBF = 1/(Fclk * Fin *Td)
Td = critical time window(the addition of setup time and hold time)

so different synchroniser ckts can be built for the purpose.normally a singal or two stage ff is sufficient to increase the MTBF boundary.

yu can refer Metastable Response in 5-V Logic Circuits by texas instruments paper for further mathematical explanations.
thank you

 

[zhangpengyu]

Clock domain Crossing

FIFO is best.

 

[gold_kiss]

Re: Clock domain Crossing

You can use 2 flop synchronizer circuit. Else use handshake, but this wont allow continous supply of data to other clock domain.

Fifo is also effective mechanism.

 

[s0shinde]

Re: Clock domain Crossing

you can use schemes like 2-way handshaking and 4-way handshaking.

 

[WzWzWz]

Clock domain Crossing

Async FIFO is better, You can search "SNUG Async" to get the document.

 

[damn]

Re: Clock domain Crossing

use synchrozer

 

[beowulf]

Re: Clock domain Crossing

For data bus, use a flop synchronized single bit control signal to validate the data bus.

Section 3.2 in this paper describes this very well:

h**p://cadence.com/whitepapers/cdc_wp.pdf

You should avoid signals crossing clock domains as much as possible and use 2/4-way handshaking. But in some designs, this is not possible due to high latency because of handshaking. You can use the above cct in that case.

HTH,
B

 

[funster]

Re: Clock domain Crossing

use two phase or four phase handshaking method to transfer data between clock domains or use your mentioned async fifo method.

Can any one tell different methods for transffering CONTINOUS data(not single bit,say byte or word) between 2 clk domains (other than Async FIFO).

 

[phoenixfeng]

Clock domain Crossing

USE hold register & MUX architecture or handshaking protocal

 

[megastar007]

Re: Clock domain Crossing

phoenixfeng, any special conditions should be taken into consideration for "USE hold register & MUX architecture"

 

[FLEXcertifydll]

Clock domain Crossing

for the one signal U can use double-sample FFs
for the bus U can synchronization use a syn-signal thro doble-sample FFs.