Prevent tools from inserting buffers (Design Compiler and Encounter)

[kalar]

Hi,

As the title of this topic indicates, I want to synthesise and P&R a design without buffers in order to observe the behaviour of long interconnects to the delay. Therefore, I want to know if there is any way to disable buffer insertion to my design, both at the stage of synthesis (Design Compiler - Synopsys) and the stage of place and route (Encounter - Cadence).

Kind regards

 

[ThisIsNotSam]

simply mark all buffer cells as dont_use. in sdc files you can do it with the set_dont_use command. you can also do it internally to the tool, but the syntax changes slightly from tool to tool

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simply mark all buffer cells as dont_use. in sdc files you can do it with the set_dont_use command. you can also do it internally to the tool, but the syntax changes slightly from tool to tool

on a second thought... this won't prevent the tools from upsizing cells to meet timing. in other words, the std cells will start to act as buffers.