[SOLVED] Preserving multiple instances during synthesis

[mozdzen]

I have a design in vhdl that calls a module 3 times.
When I synthesize it, I get a flat netlist.
How can I tell DC to not flatten my 3 modules?
Thanks,
Tom

 

[lostinxlation]

set_ungroup command ?

 

[permute]

design something that matters? why specifically are you concerned about a flattened design?

 

[mozdzen]

I don't want the cells of the blocks to be interspersed. I want to use relative placement groups in ICC to keep them in separate physical locations.
Radiation hardness issues.
Tom

 

[mozdzen]

OK - the set_ungroup instanceName false is the key

For example:
set_ungroup UnitInstA false
set_ungroup UnitInstB false
set_ungroup UnitInstC false

This worked for me.
Thanks lostinxlation for the tip