avt
Member level 5

I have implemented a comparator like the on in Gregorian, "Introductionto CMOS-OP-Amps and comparators" - this means on NMOS diffpair, one cross-coupled PMOS pair, and on PMOS load transistor in each branch of the NMOS diffpair.
It works quite good under typical mean conditions with 25 mV hysteresis - but when I do corner analysis the hysteresis threshold values changes signifcantly and can be higher than 100mV. As I have a spec that demands a threshold value of at least 25 mV and an upper limit of less than 100 mV - I would like to have better control of the hysteresis threshold.
Are there any passive or active measures to control the hysteresis threshold in regnerative (positive feedback) comparators - or are there better structures than the one I use with respect to hysteresis threshold ?
It works quite good under typical mean conditions with 25 mV hysteresis - but when I do corner analysis the hysteresis threshold values changes signifcantly and can be higher than 100mV. As I have a spec that demands a threshold value of at least 25 mV and an upper limit of less than 100 mV - I would like to have better control of the hysteresis threshold.
Are there any passive or active measures to control the hysteresis threshold in regnerative (positive feedback) comparators - or are there better structures than the one I use with respect to hysteresis threshold ?