preamplifier and comparators in flash ADC

[iamsailing]

hello , everyone

I am simulating the preamplifier and comparators in this paper:

A 6-b 1.3-Gsample s A D Converter in 0.35-um CMOS

the technology I am using is 0.18 CMOS.

my questions are as follows:

(1) the loads of preamplifier and first comparator in this paper are diode-connected MOS, what is the difference between the diode-connected MOS load and
the resistive load in flash ADC? from the simulation, the preamplifier with diode-connected MOS load will have lower output common level

(2) how to decide the output common level of the preamplifier and first comparator to let them(the preamplifier, first and second comparator) work correctly

(3)can anyone explain how the second comparator work in details?
for example, if the in+ port is higher than in- port, how the output get?

any of your suggestions will be appreciated

best regards
thanks

 

[raduga_in]

Q(1) the loads of preamplifier and first comparator in this paper are diode-connected MOS, what is the difference between the diode-connected MOS load and
the resistive load in flash ADC? from the simulation, the preamplifier with diode-connected MOS load will have lower output common level

A(1) Resistive Loaded preamplifiers are more linear than than the diode connected loads and definitely they will consume more headroom across them and so there will be lower output common mode level compared to resistively loaded once.


A(2) Need some more inputs about the supply voltage you have .

A(3) Second comparator works like a latch. Consider you have a back to back connected inverters. They work in positive feedback mode. M6 will try to pull them out of the positive feedback .

 

[iamsailing]

A(2) Need some more inputs about the supply voltage you have .

A(3) Second comparator works like a latch. Consider you have a back to back connected inverters. They work in positive feedback mode. M6 will try to pull them out of the positive feedback .

thanks a lot for your answer.


(1)in my simulation, the vdd is 1.8v.
the Msw in preamplifier is not used.
and in preamplifier ,in+ and in- are differential sine wave, in+ or in- are 1.15v+0.5Vpp, the ref+,ref- are 1.15v dc.
the gain of preamplifier is 3.3(10dB)
is the value reasonable?

(2)the 1st comparator should be nolinear? the output waveform of it should be 0.*v--1.8v or just magnify the input linearly?

(3)to let the 1st and 2nd comparator work well, the clk signal should be 0-1.8v or
others amplitude?

best regards