Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

PowerPAD Thermally Enhanced Package

Status
Not open for further replies.

Veronika

Member level 2
Joined
Mar 30, 2012
Messages
51
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,651
I am using PowerPAD at the first time (for TPS51200 voltage regulator). Am I right that the Solder Mask should not be present over the area of the exposed thermal pad of IC?
One more thing, PowerPAD vias should be added to the footprint itself or during the routing the design?
If you have same picture to represent the correct footprint of IC it would be helpful!
Thank you in advance!
 

FvM

Super Moderator
Staff member
Joined
Jan 22, 2008
Messages
47,445
Helped
14,036
Reputation
28,325
Reaction score
12,686
Trophy points
1,393
Location
Bochum, Germany
Activity points
275,953
Am I right that the Solder Mask should not be present over the area of the exposed thermal pad of IC?
Yes, the pad is supposed to be soldered.

One more thing, PowerPAD vias should be added to the footprint itself or during the routing the design
Preferably in the footprint. There are different recommendations for the design of the "thermal" vias. In most cases, small open vias (<= 0.3 mm) are acceptable. They will however drain part of the solder. Some assembly houses suggest plugged thermal vias, particularly for QFN like packages.
 
Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top