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Power Supply Rejection Analysis of LDO Regulators

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onteri

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ldo power supply

Hi everybody,

I used Cadence to simulate two designs of linear regulators... One used a PMOS device as the pass transistor while the other used a NMOS pass transistor. The error amplifier had same gain.

The plot of PSR show that there is a peaking in the response. However the peak for PMOS pass transistor is -5dB but for NMOS its -25 dB. Why NMOS has better PSR peak than PMOS?

I would appreciate your help. Thanks
 

analysis of low dropout regulator

Did you use the NMOS as the source follower model? if that is the case you will have better performance from NMOS.
 

power supply rejection ldo

yes I used NMOS as source follower and I understand that I got better performance. Can you explain it in a bit more detail why the improved performance?

Added after 26 minutes:

I guess its because that using NMOs gives a low output impedance over wide frequency range as compared to PMOS ?
 

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