awais2451985
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Hi,
In my design i synthesize the VHDL description using Synopsys Design Compiler and got the following figures for Power Consumption on 45nm standard cell asic tecnology.
1) Total dynamic power = 36.1 mWatt
2) Total leakage power = 1.20 mWatt.
Now, i want to estimate the expected power consumption (keeping in view these numbers for 45nm process) for next generation technologies
e.g 32nm, 22nm, 14nm, 10nm, 7nm and 5nm technologies. Can anyone suggest me what is the exact formula or trend of power scaling (both dynamic and static) w.r.t feature size. Any relevant material showing examples would be really helpful. Thanks in advanced.
In my design i synthesize the VHDL description using Synopsys Design Compiler and got the following figures for Power Consumption on 45nm standard cell asic tecnology.
1) Total dynamic power = 36.1 mWatt
2) Total leakage power = 1.20 mWatt.
Now, i want to estimate the expected power consumption (keeping in view these numbers for 45nm process) for next generation technologies
e.g 32nm, 22nm, 14nm, 10nm, 7nm and 5nm technologies. Can anyone suggest me what is the exact formula or trend of power scaling (both dynamic and static) w.r.t feature size. Any relevant material showing examples would be really helpful. Thanks in advanced.
