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Power reduction by technology scaling?

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eexuke

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Dear all,
If the technology is scaled down, for the same design,how about the reduction of power?
For example,the same design under 0.35 and 0.13 technology,does it mean the power is also been reduced to 0.13/0.35? What's the general rule of power reduction when technology is scaled down?

Many thanks!
 

hoangthanhtung

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Please reference the texk book of Prof Sung Mo Kang CMOS Analog Intergrated Circuit, Design and Analysis"
 

archillios

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I think for the same design,we can estimate the power reduction ratio by
square(vdd1/vdd2)*(C1/C2)
C1/C1 can be estimate by the line width.

a gross estimation
 

eexuke

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hoangthanhtung said:
Please reference the texk book of Prof Sung Mo Kang CMOS Analog Intergrated Circuit, Design and Analysis"
Hi hoangthanhtung,
Do you mean "CMOS Digital Integrated Circuit, Design and Analysis"? This prof has not written any Analog books...
 

Yun Lin

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archillios said:
I think for the same design,we can estimate the power reduction ratio by
square(vdd1/vdd2)*(C1/C2)
C1/C1 can be estimate by the line width.

a gross estimation
C1 and C2 is not only line loading, but also include the gate loading
 

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