Power-on-reset for flip flops?

[MrCravon]

I anticipate a problem using D-flip flops in my circuit and powering up my system where i don't know what state the flip flops are in after the power up. I was wondering if i could implement a simple power-on-reset like shown below in order to ensure the flip-flops always powering up in a reset state? Will it work? I mean, will it need an edge to reset? Or is holding the R-input low after power on sufficient?



Also, what is best to do with the S-input if i don't use it? Just tie it to VCC?

 

[srizbf]

in your circuit ,for R input, the cap (100nf) in parallel with R9 is redundant.
also , you need not have two caps( 10nf and 100nf in parallel in R input).
one 100nf is sufficient.

the circuit will be in reset state for approx 1millisec.

for S input , just tie it to VCC.

 

[MrCravon]

The two 100nf capacitors where suggested somewhere I was reading about this to compensate for variations in VCC. Should I just remove them?

 

[srizbf]

compensating variations with capacitor , will also have effect on resetting time.
but in this case , you can just remove that across R9.

 

[KlausST]

Hi,

You say simple.. It uses 5 (4) devices.

Why not use a single reset device? Like LM809. It includes a defined threshold voltage and it includes a defined delay time.

Btw: Using one single capacitor to GND gives the expected filter, using two capacitors will eliminate the filter. Using two capacitors makes no sense.

Hope this helps

Klaus