Power gating in synopsys

[anuradha.verma]

My VHDL design contains one main control FSM and 4 sub modules connected to it.I want to use power gating technique to on/off that sub modules and control for this comes from main FSM.how to implement that power gating transistor.I will be using the synopsys deign compiler and IC compiler tool.

i have the gate level netlist from the design compiler.how can i get the transistor level netlist from the synopsys tool so that i can manually insert the transistor.

 

[gck]

Hey
You need to create a UPF file as an input to dc_shell. UPF file contains the details of power domain, and here you can use "create_power_switch" command to do that. You also need to add isolation cells.
Just man these commands for further information,