Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
yes you could with the CPF flow.
for power gating you need:
-a power switch which is a macro-analog component.
-isolation cell, AND gate could be enough (required).
-flop with retention value (not mandatory, depends of your design/functionality)
With the CPF, you will define which part of your design could be power on/off, and the tool will add isolation cell from/to this part, and you could request to change all flop into flop-with-retention, if your require to preserve the value during the power-off.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.