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Power estimation after synthesis and Place-&-route

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naderi

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Dear all,

In my design, total power consumption estimated after synthesis by Cadence-BuildGates is:
Internal Cell + Leakage + Net =
0.2904 + 3.9775 + 0.3833 = 4.6512 mW

While, after place-and-route, Cadence-Encounter reports:
Total leakage power = 337395.002511uW

Can anyone tell me why there may be such a diffence? what might be wrong?

Thanks,
Ali
 

2 reasons:

(a.) Synthesis works in "ideal clock mode" before CTS. So it cannot see the clock buffers because they have not been inserted yet. After P&R the whole clock tree is implemented (actually, it is there after CTS), and this changes the power (even leakage, because of clock gating)

but the most important reason is..
(b.) Leakage power is dependent on the activity of your circuit. Be aware that "activity" for power analysis consists of 2 (!) parameters for each node: P-switch which is the probability that the node will switch, and P-high (or P-low) which is the probability that a node is in the high (or low) state.

The leakage power of a gate is very dependent on the state if the inputs. A 3-input NAND, for example, has lots of different input states that all give the same output state - but each imput state will cause a different leakage in the NAND, and the difference is very big.

So, if Build-Gates is assuming a different activity (P-high) profile for your design than Encounter, they will get different power numbers.

To get the two tools to give the same results, you must at least make sure they are using exactly the same activity patterns (even for leakage power!!). But, unfortunately, even then they will not agree, because Build-Gates cannot see the clock distribution network and Encounter can.
 

    naderi

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