Power-down and startup circuit for bandgap?

[triquent]

bandgap static start up

Is that possible to design the power-down and start-up circuit for the bandgap voltage reference at the same time? When I add the startup circuit for my bandgap, then the power-down isn't work anymore. Anyone can recommend the paper or examples about badgap with both of power-down and startup function?

 

[qutang]

partial power-down of a circuit

I think u can add the power-down at the current mirror?

 

[steer]

The most straightforward solution is put a big transistor that cuts down your supply rail.
This would be your power down.

 

[codec]

You should design the power-down and start-up circuit for the bandgap voltage reference at the same time.
Several types of Start-up circuits for CMOS BGR are for your choice.
1. Cap. based Start-up
Tha capacitor is initially zero which leads to the current generation in BGR loop and consequently, current mirror starts to charge the capacitor. Finally, the capacitor does not impact the main circuit any more.
2. Threshold of transistors
3. Partial current drops into PNP
Start up circuit provides partial current even after the BGR is normally triggered.

 

[ambreesh]

In diode connected PMOS have a switch that shorts the drain and gate.
Also connect a switch that shorts the gate of the PMOS to VDD.
Open the switch between gate and drain and close the switch between supply and gat during power down.
PMOS moves to cutoff.
I would use a static startup circuit. So your BGR may not consume power but startup would in power down mode.
U could have some similar logic in start up also.
hope it helps

 

[sergeyr77]

Use nmos transistor conrolled by power_down signal connecting all gates of nmos transistors and gnd. It prevents current sinking. At the same wave put pmos transistor (switch) controlled by (power_down)' signal connecting all gates of pmos transistors and vdd. It prevents sourcing from vdd. When logic signal power_down comes all current pathes from vdd to gnd are broken. At (power_down)' the circuit and it start up function in regular way.
(power_down)' = not(power_down), use invertor for it generation.

 

[mady79]

Pmos whose gate is grounded in start up mode can be connected to power down signal .When power down =0 it act as a regular start up circuit ,when power down=vdd then there is no leakage path at all .

 

[paladinzlp]

triquent:
Can you download the power-down circuit to here!
Thanks