Power DMOS Thermal resistance Vs Current distrbution

[jumbodas]

How will the Junction to case Thermal resistance vary when same power is fed to mosfer with following current distribution modes.
For example 10W power

A) Mosfer fully turned ON Id =20Amp Vds = 0.5V
B) Mosfer off Vgs =0, avalanche condition Id = 0.1amp Vds = 100V
C) Mosfet off Vgs = 0 Body diode forward. Id = -10amp Vds = -1V

 

[dick_freebird]

The location within the device volume where power is shed differs. Breakdowns tend to more concentration and no uniformity of power than ohmic or forward junction conduction. Avalanche behavior and location and power density vary a lot with construction - do you punch through the neck, up on top and far from heat removal and right up in the business, or do you over-field the drift region (and huge volume and thermal path difference there, VDMOS vs LDMOS).