Yes - it will probably reduce power consumption.
What are your goals? FPGAs are relatively power hungry
The tool shows most of estimated power dissipation for the present design due to leakage current, mainly inside the core. This part doesn't depend on the design, as long as the FPGA doesn't implement power down of unused logic elements. The feature may be available in low power devices, but unlikely in Virtex 5 family. Choosing a smaller device can safe quiescent power.