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Power dissipation on FPGA

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MSAKARIM

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How can i control power dissipation of a design implemented on FPGA ?
 

Flick the off switch would be a good start...
 

I don't know what do you mean ?
.
If i decrease the operating frequency this will be helpful ?

Yes - it will probably reduce power consumption.
What are your goals? FPGAs are relatively power hungry
 

Yes - it will probably reduce power consumption.
What are your goals? FPGAs are relatively power hungry

I want to know how can i reduce dynamic and quiescent power for a certain design implemented on FPGA ? Is this depending on Code (VHDL or Verilog) or on FPGA's construction or on what ?

I get this analysis Using Xiliinx tools ,also i need some help to understand all power values in the following image.
Untitled.png
 

Power is dissipated when signals change. The tools you have estimate the power usage. Short answer - less logic will probably dissapate more power.
 
The tool shows most of estimated power dissipation for the present design due to leakage current, mainly inside the core. This part doesn't depend on the design, as long as the FPGA doesn't implement power down of unused logic elements. The feature may be available in low power devices, but unlikely in Virtex 5 family. Choosing a smaller device can safe quiescent power.
 
The tool shows most of estimated power dissipation for the present design due to leakage current, mainly inside the core. This part doesn't depend on the design, as long as the FPGA doesn't implement power down of unused logic elements. The feature may be available in low power devices, but unlikely in Virtex 5 family. Choosing a smaller device can safe quiescent power.

Ok, thanks
Could you please help me to understand the thermal properties that is described in the previous image?
 

Thermal properties? Trivial calculus:

junction overtemperature = total power * thermal resistance junction to ambient (TJA)
actual junction tempeature = ambient + overtemperature
maximum ambient = 125 °C - junction overtemp
 
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