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I want to know how can i reduce dynamic and quiescent power for a certain design implemented on FPGA ? Is this depending on Code (VHDL or Verilog) or on FPGA's construction or on what ?
I get this analysis Using Xiliinx tools ,also i need some help to understand all power values in the following image.
The tool shows most of estimated power dissipation for the present design due to leakage current, mainly inside the core. This part doesn't depend on the design, as long as the FPGA doesn't implement power down of unused logic elements. The feature may be available in low power devices, but unlikely in Virtex 5 family. Choosing a smaller device can safe quiescent power.
The tool shows most of estimated power dissipation for the present design due to leakage current, mainly inside the core. This part doesn't depend on the design, as long as the FPGA doesn't implement power down of unused logic elements. The feature may be available in low power devices, but unlikely in Virtex 5 family. Choosing a smaller device can safe quiescent power.
junction overtemperature = total power * thermal resistance junction to ambient (TJA)
actual junction tempeature = ambient + overtemperature
maximum ambient = 125 °C - junction overtemp
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