Power Difference between Analog Simulation and RTL complier estimation .

[graphene]

Hallo,

I am creating a standard cell library. I did analog simulation for cell design and estimated power values for the cells , lets say, NOT, NOR and NAND and I have their power values for static, dynamic, etc.

Now based on that I created library file, and used that in RTL omplier for single cell designs and when i estimate the power it goes up to several orders and I am clueless of why this is so.
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Any suggestions or ideas ??
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The operating conditions are verified for the same such as Freq, VDD, Load Cap., etc.
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Ex: for a 10nW in Virtuoso (Analog) estiamtion the equivalent estimation comes upto 80-90 nW in RTL power estimation.

 

[rca]

Well RTL compiler power estimation is based on the liberty value, and the create_clock which define the frequency and load is based on the LEF or wire load, and toggling is dependent of the power estimation, average value determined by the tool, or based n SAIF file.
There is some tool to generate the liberty.

 

[graphene]

Hallo rca, thank you for the infos.

1) I am creating standard cell library.. I have my library characterised i.e. i have my own .lib file generate for my cells using Altos Liberate.
I dint create a LEF for the design yet. I am estimating the power without LEF and wireload. I thought I can manually define the loads to the RTL compiler. Is it a wrong approach ?? Should I include LEF infos to estiamte power in RTL compiler ?

2) Also i read in Manual that Toggling rate is 0.02 and probability is 0.5 .... hence without a test bench and using this as default will my estimation be reilable.. ??