[SOLVED] Power Consumption of Emulated MCUs

[BurnAndLearn]

I am interested in supplementing a low-power microcontroller (MSP430) with an FPGA (undecided) to add 8 custom timers. My experience with FPGAs is limited (1 semester), but I do know that it is possible to emulate certain processors within an FPGA, so I could theoretically end up with a single-part solution where an MCU is wired up to these 8 timers inside the FPGA. My question is: what is the power consumption of an FPGA 'emulating' a processor vs the power consumption of the real processor? I suspect I will be better off adding a small FPGA to an MCU rather than combining them, but I would like to know the thoughts of some folks with real experience. Also, how does emulating a processor in an FPGA affect its maximum clock speed relative to the actual processor?

Thanks!

 

[andre_luis]

I am interested in supplementing a low-power microcontroller (MSP430) with an FPGA (undecided) to add 8 custom timers

Why don´t you simply insert an IP microcontroller core inside the FPGA with as many Timers as you want, so that you can take the estimation of the power consumption of whole circuits at a single simulation ?

 

[BurnAndLearn]

Is it that simple to just simulate the whole thing and get the power consumption? My post already suggested inserting a microcontroller core inside the FPGA. I just have never done this personally so I am asking for words of wisdom from people who have. As I don't have a ton of experience with FPGAs (99% of what I do everyday is embedded C and circuit design), the amount of work involved in just getting my bearings and putting HDL on some hardware is huge (no point in doing all of that to discover some obvious shortcoming(s) a forum member might be able to easily point out).

I took two courses on FPGAs in school and that was about 3 years ago. I don't have an FPGA board to even attempt this with. I will need to read a lot to determine my needs. In school, we used Altera DE2 boards for everything.

Thanks for taking the time to help me.

 

[dpaul]

My question is: what is the power consumption of an FPGA 'emulating' a processor vs the power consumption of the real processor?

This is more like asking which implementation technology has more power consumption - ASIC or FPGA. To directly answer your question, a real processor (an ASIC) has less power consumption compared to the same processor implemented in FPGA. A simple search will come up with many articles explaining why ASICs have less power consumption than FPGAs..
Implementing a processor in FPGA just gives you the flexibility to modify, verify and play around with your design. Engineers make sure that their design is working as expected on bare-metal.

Also, how does emulating a processor in an FPGA affect its maximum clock speed relative to the actual processor?

Again in an actual processor implemented as an ASIC you have the freedom of minimizing delays and using custom place & route, which can yield a higher max. clock speed compared to the FPGA implementation.

 

[BurnAndLearn]

This is more like asking which implementation technology has more power consumption - ASIC or FPGA.

I wasn't asking which technology consumes more; I was asking how much power an FPGA implementation consumes vs ASIC. It is obvious that FPGA is higher (otherwise there would be no point in using ASIC), but has anyone actually tested their MCU core on an FPGA vs the ASIC version of the same? If so, is there an approximation to determine the difference? Is it 10x the power or 1,000,000x the power? I have no idea and I thought someone here might.

 

[ads-ee]

It's highly dependent on the process used. FPGAs have much higher leakage currents so right there you're MCU circuit is already using more power just sitting there without a clock running. If all you are discussing is the difference in dynamic power of the processors then that could be determined if you had both the netlists for the ASIC with it's libraries, and the netlist of the FPGA, and run power analysis on both.

So in short no there is no magic way to find the power difference. You normally look a the power and decide based on the requirements of your system if you can afford the extra leakage current and greater flip-flop dynamic power requirements of an FPGA implementation of a micro. There is also a big cost trade off, micro+smaller FPGA << bigger FPGA (with micro built in). As many micros used are < $1 they are a lot cheaper than using an FPGA to do the same job.

 

[BurnAndLearn]

Alright, thank you. I am now favoring the MCU + small FPGA approach.

For each of the 8 "timers" I wish to add, I will need 1x 24-bit counter, 1x 12-bit counter, a way to stop the 24-bit counter when the 12-bit counter reaches a certain value. The 24-bit timer/counter will operate at up to 24Mhz. To me, this seems like very little hardware. What hardware would you suggest I use to implement this, based on easy entry and accessible software tools? It would be great if I didn't need to incorporate some BGA monstrosity into my layout, but I can deal with that if needed. Some sort of QFP part would be ideal. Something that is available on reasonably priced dev board is mandatory. Is 3.3V I/O available in FPGAs or do I need to level-shift everything? This project is in it's infancy, so proof of concept is the goal right now.

Thanks again for your time.

 

[vGoodtimes]

You might look into single chip solutions from atmel and similar where a low-power uC is combined with low-power/performance FPGA fabric. CPLD's might also be suitable. Cypress also might have some PSOC that has the required features.