power consumption in FPGA for 50MHz QPSK modulator

[asraf]

what is the power consumption in FPGA for 50MHz QPSK modulator?
whether the power consumption will reduce if the QPSK modulator implemented in fully digital domain?
tq
-asraf-

 

[Lt_Garillios]

That will depend completely on how you implement it, what type of FPGA you use and how optimised your hdl code is.

 

[asraf]

i would like to get rough or general idea here.can you help me? what is the power consumption if in sparten 3e FPGA board within 50MHz?