Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

power consumption in FPGA for 50MHz QPSK modulator

Status
Not open for further replies.

asraf

Junior Member level 3
Joined
Nov 22, 2010
Messages
30
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,589
what is the power consumption in FPGA for 50MHz QPSK modulator?
whether the power consumption will reduce if the QPSK modulator implemented in fully digital domain?
tq
-asraf-
 

Lt_Garillios

Newbie level 5
Joined
Apr 21, 2011
Messages
10
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,283
Activity points
1,336
That will depend completely on how you implement it, what type of FPGA you use and how optimised your hdl code is.
 

asraf

Junior Member level 3
Joined
Nov 22, 2010
Messages
30
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,589
i would like to get rough or general idea here.can you help me? what is the power consumption if in sparten 3e FPGA board within 50MHz?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top