Power Clamp for ESD Chip Protection

[dmfrl]

I wonder why not PMOS is used as shorting component between VCC and GND rather than NMOS which gate is connected to inverter chain?

Does anyone have an idea?

 

[neils_arm_strong]

can you clarify the question ?
Are talking about using the PMOS as a pull-up device ?

 

[dmfrl]

Okay in common power clamp for esd protection NMOS transistor is commonly used as Pull-Down of ESD current from VDD to VSS rail. I wonder if PMOS transistor can replace NMOS transistor in this situation?

 

[rubink]

Yes sometimes pmos devices are used. They will need a larger area than nmos for the same ESD current. They are less prone to snapback breakdown which I assume is why they are sometimes preferred.