Power amplifier design for input matching

[dpxiao333]

For power amplifer input matching, does it matter to put the bias network closer to the device or put the matching network closer to the device?.

I mean seen from the input the sequency is

INPUT+BIAS NETWORK+MATCHING NETWORK+DEVICE

or

INPUT+MATCHING NETWORK+BIAS NETWORK +DEVICE

I find some paper first match the device in the package and then design the bias network. If it is better than the other way, can somebody explain the reason?

Many thanks.

 

[madengr]

The device is matched inside the package since the input impdeance is so low due to gate capacitance, sometimes < 1 Ohm. The farther you mave away from this capacitance the harder it is to match due to losses and phase shift. It's often impracticle to fed the bias inside the package since the inductor is physically too big to fit inside.

If your bias network provides low frequency stability, and your matching network is band-pass or high-pass, then the bias network must be next to the device. If your bias network is not high enough impedance at RF then it must be treated as part of the device.

If it is high enough impedance at RF, and you have a low-pass matching network, then you can place it anywhere along the matching network.

Soemtimes you need to pulse the device on so you don't want to feed the bias pulse through the matching network.

Placing the matching network as close to the device (measurement reference planes) as possible is best however sometimes you can't do this.

 

[dpxiao333]

Many thanks for the explainations.

In conclusion, does it mean there shall be no difference in case both two configurations can be used?

However, the paper I had (see attached) mentioned with internal matching the output power increased.

if the measurement plane are following:

without interal match : at the device plane
with internal matching plane: at the interal matching plane.

Compare this two conditions at the same absorbed power level, the one with interal matching network should have lower output power due to the loss of the matching network, which is different fromt the conclusion of the paper, unless it compares at the same inject power.

I think the internal matching is better is mainly due to the reduce of loss of the matching network (by put matching network as close as possible to the device) which increases the absorbed power at the device plane?

 

[madengr]

The paper shows results for "internal matching" and "no internal matching". I'll assume that "no internal matching" means no matching whatsoever; they did not indicate they used external matching. They results are not suprising since the input impedance is ~ 1 Ohm. I'll also assume they kept the same drive level. If they drove the unmatched device harder then the curves may have matched.

The internal matching will always be better. For instance, lets assume the lead of the package has 0.1 Ohms resitance. If you put 0.1 ohms between the matching network and chip, 10% of delivered power will be dissipated in the lead since it sits between a 1 Ohm source and load. However if the matching network is adjacent to the chip, then the lead is between a 50 ohm source and load so it's resistance is insignificant. Moving the matching network as close as possible to the chip is best so the input power does not get wasted.

Now the intersting part. The core of a FET is a voltage controlled current source. It does not care about power flowing into the gate, just the voltage across the gate capacitance. The gate is comprised of two resistances; resistance of the gate metalization and a dynamic resitance due to the lossy dielectric of the gate capacitance. This is all lumped into one resistor in series with the gate capacitance (at least in most models). The output current is proportional to the voltage across the gate capacitance. That undesired resistance is what dissipates the power. Now an ideal FET would have no gate capacitance, but a real one does so you have charge flowing in and out of the gate. That current through the gate reistance is where the power is dissipated.

So when you match the gate you don't want the best impedance match. You want the optimum voltage waveform across the gate capacitance. That is why the peak output power usually never corresponds to the lowest mismtach between gate and source. In fact, you can add harmonics to the input and shape the waveform to get the optimum drain current shape. That's whats behind harmoinic source pull.

Interesting stuff.

 

[dpxiao333]

That is really interesting and indeed ture, which I never think about it in detail. Thanks a lot.

Many text books mention for power amlifier design: the output is matched at optimized load from loadpull measurement and the input is designed to be conjugated matched. So I took it for granted, that the input is always conjugated matched.

For FET device which are voltage controlled, the input match should be designed to maximize the voltage swing at Cgs.

And the absorbed power is actually the dissipated power from the resistor since:

Pin=P_reflected+P_dissipated.

But I think there is a trade-off: For power amplifer design it is also important to increase the Transducer gain (Gt=Pout/Pin). So on one hand we should maximize the voltage swing at Cgs, on the other hand we should keep the reflected power low.

Madengr do you have any insight about it?

Thanks again.

 

[qureshi]

Hi all,


Can anybody tells how, we can calculate the input impedance, and input power of an Antenna.........

Plz reply,,,,,,,,who knows about very well.



Regards!

 

[madengr]

All I can really comment is that when tuning up devices there is a point of optimum source impedance that yields the highest output power. I have been able to get slightly more output power with this source impedance than a conjugate match. These are on big FETs, 30 - 60 Watt devices. I'm talking about < -20 dB return being considered a conjugate match, versus -10 dB return loss.

Now in reality it's hard to get a conjugate match over any appreciable bandwidth since the FET input impdeance is so low. Add another stage to the input matching network and you have just added more loss, probably more than the mismatch loss you are trying to compensate for. If you really need low input return loss you can use 90 degree hybrids to run two stages in quadrature.

I'd really like to take some measuremnts to quantify this behaviour however real work gets in the way. Until then I really don't have any proof of measurements.

Now Maury calls this "waveform engineering" with the LSNA. Using this, combined with load pull de-embeded directly to the FET chip, one can proably get a good picture of whats going on.

**broken link removed**

 

[vfone]

Not always in a PA design the input match is designed for conjugate match. There is a trade off between gain, noise power, and input return loss bandwidth.

Also there is a trade off designing the output match for maximum output power vs good efficiency.

For good performance and to use minimum number of components is good to integrate part of the bias components into the input/output matching network (if is possible)