postive edge triggered D flipflop

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Bhuvanesh123

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In the above circuit if clock(CLK 1) goes from 0 to 1 and input D =0 ,this makes Q=0.
It is stated that when the clock is at HIGH(1) any further change in input does not affect output,how it is so .Can you explain me please.Thank you in advance
 

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I suggest you describe each signal of the above logic circuit in a timing graph.
You'll see how it works.
 

Bhuvanesh123 said:
It is stated that when the clock is at HIGH(1) any further change in input does not affect output,how it is so
Click to expand...

As said, would be necessary perform some analysis step by step, or even simulate. The waveform bellow confirms that the circuit is really not sensitive to changes at DATA pin while CLK stay high.
 

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