Post synthesis Vs pre synthesis

[oursriharsha]

post synthesis simulation pre synthesis

Hi all !
How was the weekend ..?

Can you please explain :

1) what exactly happens during pre-synthesis simulation and post synthesis simulation?
(Netlist generation etc etc is ok , i need something in detail)

2) what care one should take while coding , so that the logic/design works the same wy in both cases of pre and post synthesis simulations.?

(I have a prob with my code which works solid presynthesis and post synthesis shows no output )


IDE : Libero v 8.5 (ACTEL).
Simulation tool : Modelsim
synthesis tool : Synplify

--harsha!

 

[shastri.vs]

I dont know about Synplify , but in Xilinx ISE you will get a file which has timing information included after post synthesis. These timings are calculated by the synthesis tool and hardcaded in the file along with the functionality.
One need to simulate this for timing simulation i.e post synthesis simulation.

Now what output you are getting ?? are getting unknown values or some values that are not expected ??

 

[oursriharsha]

i get X s
in place of data..