Post-synthesis STA with PrimeTime

[Atre]

sta fanout

Hello,

I have a problem concerning STA on a design after synthesis.

In DC, I set ideal_network on reset pin.
In PrimeTime it seems I can not do that and it reports lots of transition violations.
How can I tell to PrimeTime that reset net is ideal.

Generally speaking, how can I do STA on post-synthesis design, using the constraints from DC???

Hope someone can help!

Best regards,
Atre.

 

[ldm]

sta prime time

just stack the reset at inactive level...

 

[ami]

get_nets with high fanout in dc

Just set_false_path from that_reset_signal

 

[xworld2008]

in general, pre-layout STA is used for check constraints integrality. and PT can't set_ideal_net for high fanout nets. So if you need check for prelayout, you can w
rite a scripts to set high fanout nets(exp.> 100) as ideal nets.
in this script:
(1) first, need find all fanout nets,
(2) set_load 0 -subtract_pin_load [get_nets $net]
set_resistance 0 [get_nets $net]

 

[Atre]

in general, pre-layout STA is used for check constraints integrality. and PT can't set_ideal_net for high fanout nets. So if you need check for prelayout, you can w
rite a scripts to set high fanout nets(exp.> 100) as ideal nets.
in this script:
(1) first, need find all fanout nets,
(2) set_load 0 -subtract_pin_load [get_nets $net]
set_resistance 0 [get_nets $net]

Thank you. Problem solved!

 

[jjww110]

set drive 0 can also solve your problem!!