Post synthesis simulation

[tariq786]

post synthesis

Hi friends,
Does anyone know how to do post synthesis simulation using modelsim when i have synthesized my design using Synopsys design compiler. Since i have essentially mapped my original RTL design into asic gates, i am wondering how to do this simulation and what files (simulation libraries) are necessary?





any useful pointers or links shall also be appreciated.

Thaks

Added after 39 seconds:

sorry i misspelled thanks

 

[naveenkrishnan]

was ist post-synthese

You need the following to do netlist simulation:

1. The design netlist, written out from synopsys design compiler in verilog format
2. The library files for simulation. These files must correspond to the library files used to synthesize the design.

Feed the above to your verilog simulator and you are on the way to debugging your netlist now.

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