Post Simulation /pre simualtion

[santuvlsi]

Hai friends,

What is meant by

Post simulation/presimulation
Post layout/pre layout.

 

[avimit]

pre means before post means after.
I haven't heard post-simulation and pre-simulation before. It doesnt make much sense to me.
pre layout and post layout is referred to netlist i.e pre layout netlist and post layout netlist.
pre layout netlist is netlist before the layout
post layout netlist is nelits after the layout, which contains clock tree buffers, hold buffers, and may be quite different to per layout netlist, but yet, functionally equal to per layout netlist
Kr,
Avi
http://www.vlsiip.com

 

[megastar007]

i didnt heard abt pre and post simulation but i guess it could be functional simulation and Gatelevel simulation

 

[santuvlsi]

Dear avmit,

Nice explanation, Rather a small thing has to be cleared

pre layout is netlist before layout you have said ok

What do u mean before Layout do you mean the tnetlist

obtained after floorplanning, parastic extraction,

why becos we get netlist of layout is obtained once we layout and then run.

Pls clear

Added after 1 minutes:

Dear avmit,

Nice explanation, Rather a small thing has to be cleared

pre layout is netlist before layout you have said ok

What do u mean before Layout do you mean the tnetlist

obtained after floorplanning, parastic extraction,

why becos we get netlist of layout is obtained once we layout and then run.

Pls clear

 

[anantha_09]

hi

we normally hav

1. simulation: of unmapped(pre synthesis) logic. here design is interms of RTL.

2. post synthesis simulation: simulation of mapped design. i.e gate level net list simulation. this also called pre layout simulation.

3. post layout simulation: simulation after the backend steps(floor plan, p&r, layout, clock tree etc etc etc ) as stated clearly by avimit.

gud luck
anantha

 

[avimit]

Hi,
I have not quite understood what exactly you are after?
But yes I will explain what I mean by pre-layout.
Pre-layout netlist is a netlist which comes out of a synthesis tool, and is before floorplaning or any parasitic extraction. It comes straight out of say design compiler. Its an input to floorplanning tool. or in general terms it is an input to layout or back-end flow.
Hope it helps,
Kr,
Avi
http://www.vlsiip.com

 

[anantha_09]

hi

I think u should go through some of the following sites they are really helpfull:

www.asic.co.in

www.asic-world.com

www.vlsiip.com

and do refer asic chip synthesis by himanshu bhatnagar (available in edaboard)

u get good knowledge

cheers
anantha

 

[sarath51]

post lay out simulation after placement and route SPEF is extracted for timing and this is used with simulation tools to do gate level simulations

 

[vlsichipdesigner]

Dear Santu,

my 2 cents in this Discussion Topic,

Appreciate the contribution by avimit.

Pre-layout Simulation:

1. RTL Simulation : To Ensure that the design works for functionality.
2. Gatelevel Simulation: Now RTL is synthesized and we have gatelevel netlist.
We use this gatelevel netlist and perform simulation.
To Ensure Functionality and To ensure meets the specific Timing Requirements, we perform Static Timing Analysis with the gatelevel netlist.
3. ATPG Simulation : We also take the Gatelevel Netlist and perform zero delay simulation and perform ATPG simulations.

Post-layout Simulation:.
Now we have perform layout (place and route) , Now we have a kind of real physical Design stuff for our design.

We perform the Extraction(To extract the Resistance/Capacitance) values of the Design in the format called as SPEF(Standard parasitics Extraction Format).

We use the Place & Route Verilog Netlist and the Extracted SPEF file in the Static Timing Analysis and generate the SDF(Standard Delay Format) file.

1. Dynamic Gatelevel Simulation : Use the Place and Route (verilog netlist) and the SDF file and the test vector on our Design testbench and ensure that the design works after layout.
2. Static Timing analysis : The place and route(verilog netlist) and the SPEF file and the SDC(design constraints file) is used and perform the timing analysis.
3. Power Analysis : Perform the power simulations and ensure the design meets power requirements.
4. Noise Analysis : Perform crosstalk Noise simultions and ensure the design is immune to Noise.
...

To understand about ASIC Design concepts (STA/SDC/SPEF/Place and Route....)
https://www.vlsichipdesign.com/knowledgehome.html

To understand all the Verification Methodologies.
https://www.vlsichipdesign.com/asic_verification.html

Praise the Lord

best regards,
vlsichipdesigner
https://www.vlsichipdesign.com
[learn ASIC chip designing for Free]