pOST ROUTE SIMULATION PROBLEM

[prasanthri]

I have written a code for D-FF in VHDL. When I performed the post-route simulation I got an unacceptable delay in the output. I used a clock of 10 ns period (100 MHz)as the input clock. But the output is changing only about 6 ns after the positive edge of the clock for which it is designed to change. I am using Xilinx ISE for synthesis and Modelsim SE for simulation. Here is the code I have written...

Code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dff is
Port ( data : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
q : out STD_LOGIC);
end dff;

architecture Behavioral of dff is

begin

process (clk,reset)

begin
if reset= '1' then
q<='0';
else

if rising_edge(clk) then

q<=data;

else null;
end if;
end if;

end process;

end Behavioral;




Test Bench

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY tb_dff_vhd IS
END tb_dff_vhd;

ARCHITECTURE behavior OF tb_dff_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT dff
PORT(
data : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
q : OUT std_logic
);
END COMPONENT;

--Inputs
SIGNAL data : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL reset : std_logic := '0';

--Outputs
SIGNAL q : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: dff PORT MAP(
data => data,
clk => clk,
reset => reset,
q => q
);

reset<='1','0' after 100 ns;

data<=not data after 200 ns;
clk <= not clk after 5 ns;

END;

 

[banjo]

The Xilinx placer should have located the flop in the IOB. Therefore, it should not have a large delay. This delay most likely has two possible causes.

1. It is only an artifact of the simulation. Try reducing your simulation timestep. I have had to use timesteps as small as femto seconds to get accurate results with some simulations using ModelSim.

2. Perhaps this is due to the default SLOW slew rate limited IO driver. Try changing the IOB attribute to fast and see if it improves. You can open the design in FPGA Editor and verify that placement was in an IOB and also verify what speed driver was chosen.

 

[babaship]

**broken link removed**