post route simulation error

[vinodkumar]

Hi everybody,
i got the following error when iam doin PAR using questasim,for simple ram implementation,i have instantited BRAM.
iam able to debug even with chipscope,urgent plz.


# Reading C:/QuestaSim_6.2b/tcl/vsim/pref.tcl
# // QuestaSim 6.2b Jul 31 2006
# //
# // Copyright 2006 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND
# // PROPRIETARY INFORMATION WHICH IS THE PROPERTY
# // OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS
# // AND IS SUBJECT TO LICENSE TERMS.
# //
# do {ram168.tdo}
# ** Warning: (vlib-34) Library already exists at "work".
# QuestaSim vcom 6.2b Compiler 2006.07 Jul 31 2006
# -- Loading package standard
# -- Loading package std_logic_1164
# -- Loading package vital_timing
# -- Loading package vcomponents
# -- Loading package vital_primitives
# -- Loading package textio
# -- Loading package vpackage
# -- Compiling entity ram168
# -- Compiling architecture structure of ram168
# vsim -lib work -sdfmax /ram168=netgen/par/ram168_timesim.sdf -t 1ps ram168
# ** Note: (vsim-3812) Design is being optimized...
###### C:\Xilinx91i\vhdl\src\simprims\simprim_VITAL_mti.vhd(1):
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# ** Error: C:\Xilinx91i\vhdl\src\simprims\simprim_VITAL_mti.vhd(1): VITAL_Level0 model can use only VITAL_Level0 entities.
# (1076.4 section 3.1)
###### C:\Xilinx91i\vhdl\src\simprims\simprim_VITAL_mti.vhd(155211): END OF FILE
# ** Error: C:\Xilinx91i\vhdl\src\simprims\simprim_VITAL_mti.vhd(155211): Vopt Compiler exiting
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./ram168.tdo PAUSED at line 7

 

[nxtech]

Is your simulator license up to date and or installed in the location the tool expects to see it?