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DRC - check, that all polygons of your layout satisfy foundry design rules (polygon width, spacing, overlap etc).
LVS - extract from you layout the transistor netlist and compare it (element by element) with original netlist (it is not logical equivalence checking, but electrical equivalence). For example, after routing, you may have some shorts (no free space for roitung), so in the extracted netlist you will see these shorts, but in the original netlist - no shorts.
Tools - Calibre (Mentor), IC Validator (Synopsys) ...
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