Hi,
I am doing the whole fpga design flow on AES (Advanced Encryption Standard Core).The behavioral simulation in modelsim works fine but when i run the post translate or post map simulation in modelsim, i get 0 at the output that is my output is always 0.
Why is this the case?
Any ideas? Am i correctly simulating? or do i need to do more to simulate?
Please let me know.
there is a switch in command vsim. I think -sdfwarn.
In GUI also, in start simulation window, you can find check boxes which will be something like "diasable sdf errors to warnings" and like.