prasad1
Newbie level 4
I have created layout using cadence SoC encounter. I have saved the netlist .v file & delay file .sdf.
targeted library is faraday 180 nm. Now for doing postlayout simulations using modelSim I have added this netlist, .sdf file, lbrary files which are in present in the generic core directory by folder name verilog.
but when i start simulation
loading error is comming.
Loading work.AN3
# Loading work.INV2
# Loading work.OAI222S
# Loading work.OA222
# Error loading design
wat is the problem.
other problem is lvs check.
I have imported verilog netlist that is used in soc encounter for preparing layout into cadence virtuose(icfb).
for schematic generation but when i do lvs check the following errors are occured.
Net Listing Mode is Analog
*Error* schematic cell: june_19_1 rx_core symbol
The schematic was never extracted or is not current in the schematics editor.
Use the `Check and Save' operation in the schematics editor to correct this.
The lastSchematicExtraction property is missing.
*Error* schematic cell: june_19_1 chip_gen symbol
The schematic was never extracted or is not current in the schematics editor.
Use the `Check and Save' operation in the schematics editor to correct this.
The lastSchematicExtraction property is missing.
*Error* schematic cell: june_19_1 opsk symbol
The schematic was never extracted or is not current in the schematics editor.
Use the `Check and Save' operation in the schematics editor to correct this.
The lastSchematicExtraction property is missing.
*Error* schematic cell: june_19_1 symbol_gen symbol
The schematic was never extracted or is not current in the schematics editor.
Use the `Check and Save' operation in the schematics editor to correct this.
The lastSchematicExtraction property is missing.
*Error* schematic cell: june_19_1 iopads_t33 symbol
The schematic was never extracted or is not current in the schematics editor.
Use the `Check and Save' operation in the schematics editor to correct this.
The lastSchematicExtraction property is missing.
5 error(s) encountered, vldb not generated
Error - dfIIToVldb failed to execute
plz suggest me to resolve these problems.
thank in advance
targeted library is faraday 180 nm. Now for doing postlayout simulations using modelSim I have added this netlist, .sdf file, lbrary files which are in present in the generic core directory by folder name verilog.
but when i start simulation
loading error is comming.
Loading work.AN3
# Loading work.INV2
# Loading work.OAI222S
# Loading work.OA222
# Error loading design
wat is the problem.
other problem is lvs check.
I have imported verilog netlist that is used in soc encounter for preparing layout into cadence virtuose(icfb).
for schematic generation but when i do lvs check the following errors are occured.
Net Listing Mode is Analog
*Error* schematic cell: june_19_1 rx_core symbol
The schematic was never extracted or is not current in the schematics editor.
Use the `Check and Save' operation in the schematics editor to correct this.
The lastSchematicExtraction property is missing.
*Error* schematic cell: june_19_1 chip_gen symbol
The schematic was never extracted or is not current in the schematics editor.
Use the `Check and Save' operation in the schematics editor to correct this.
The lastSchematicExtraction property is missing.
*Error* schematic cell: june_19_1 opsk symbol
The schematic was never extracted or is not current in the schematics editor.
Use the `Check and Save' operation in the schematics editor to correct this.
The lastSchematicExtraction property is missing.
*Error* schematic cell: june_19_1 symbol_gen symbol
The schematic was never extracted or is not current in the schematics editor.
Use the `Check and Save' operation in the schematics editor to correct this.
The lastSchematicExtraction property is missing.
*Error* schematic cell: june_19_1 iopads_t33 symbol
The schematic was never extracted or is not current in the schematics editor.
Use the `Check and Save' operation in the schematics editor to correct this.
The lastSchematicExtraction property is missing.
5 error(s) encountered, vldb not generated
Error - dfIIToVldb failed to execute
plz suggest me to resolve these problems.
thank in advance