Post Layout Simulation

[AdvaRes]

Hi all,
I designed DLL using the Cadence tool Virtuoso the simulation with eldo was excellent. Is there a possibility that the DLL would not be functionnal after doing layout when performing the post layout simulation ?
The layout will be done using a standard cell lib of basic component like Transistor resistors...
In fact, I'm affraid to repeat all the work again if the response is yes ?

Thanks in advance for your replies.

 

[Teddy]

Yes it might happen. Actually your frequency and PVT performance might be changed. So it is a good idea to do post layout with parasitcs.
BUT if you had good results in corner simulation and if you do decent layout you should not have big issues and will probably say that it is fine. I recommend to resimulate the critical parts like VCO

 

[AdvaRes]

Yes it might happen. Actually your frequency and PVT performance might be changed. So it is a good idea to do post layout with parasitcs.
BUT if you had good results in corner simulation and if you do decent layout you should not have big issues and will probably say that it is fine. I recommend to resimulate the critical parts like VCO

Thanks my friend for your reply.
Could you please explain what do you mean by "to do post layout with parasitcs" and how to do it ?

 

[carv_13]

Pre layout simulations would not have the resistance and capacitance components to take into account. It helps us to find out if circuit is working functionally.

After you do layout, virtuoso allows you to do a RC extraction which contains the resistance and capacitance values ie the parasitic values. These allow you to figure out if the circuit would work when you actually get the chip done.

Is there a chance the circuit wont work after layout, drc and lvs runs?. Yes its possible. All these just prove that the circuit had been laid out correctly. But due to the effect of resistance and capacitances, there is a chance that some signals get affected and hence the circuit does not behave as expected.

-Aravind