AdvaRes
Advanced Member level 4
Hi all,
I designed DLL using the Cadence tool Virtuoso the simulation with eldo was excellent. Is there a possibility that the DLL would not be functionnal after doing layout when performing the post layout simulation ?
The layout will be done using a standard cell lib of basic component like Transistor resistors...
In fact, I'm affraid to repeat all the work again if the response is yes ?
Thanks in advance for your replies.
I designed DLL using the Cadence tool Virtuoso the simulation with eldo was excellent. Is there a possibility that the DLL would not be functionnal after doing layout when performing the post layout simulation ?
The layout will be done using a standard cell lib of basic component like Transistor resistors...
In fact, I'm affraid to repeat all the work again if the response is yes ?
Thanks in advance for your replies.