Post layout simulation error in 45nm technology.

[akchetana]

Hello everyone,
I want to perform the post-layout simulation for 6T SRAM cell in Cadence for 45nm technology. However, I am trying to perform with a simple inverter first. The DRC and LVS are cleared. Now when I try to do post-layout it shows me an error while adding the RCX file. However, the simulation succeeded for 180nm technology for the same circuit. Maybe this is because the RCX file is not attached or not found for 45nm technology. Can anyone tell me the way to attach these files?

 

[erikl]

... it shows me an error while adding the RCX file. ...
Maybe this is because the RCX file is not attached or not found for 45nm technology.

These two statements don't fit together - at least for my understanding. I think you should make it clearer: is the RCX file found and used - or not?

 

[akchetana]

These two statements don't fit together - at least for my understanding. I think you should make it clearer: is the RCX file found and used - or not?

Hello,
Let me explain it more. After clearing the DRC and LVS, I select Assura- Run RCX. In Pop up window, in the extraction tab I select Cap coupling mode as 'Coupling' , I make some other changes in other tabs. Now in the Run details, when I try to add the run file, it shows an error saying file not found. I feel we are supposed to add an RCX file. But I could not find any file with the extension .rcx.
Thank you. Waiting for the reply.

 

[Dominik Przyborowski]

In 45nm the most probably You should use PVS QRC for extraction.

 

[akchetana]

In 45nm the most probably You should use PVS QRC for extraction.

Thank you for your kind reply.
Can you explain it more? And the steps that I followed, are they correct?