Post-layout and post-synthesis STA issues.

[eng.obd_md]

Hi,
My design is working perfectly good after the post-synthesis (using DC) at clock rate of 5 ns.

In place and route(using encounter), I got 50 setup violating path. I tried to simulate the netlist and it worked but with a clock of 40 ns (might be not the corner but it didn't work with 5 ns or even 20 ns).

My question: is it possible to perform optimization here and how effective would that be, would I be able to simulate at 5 ns. Also, how can such optimization be performed?

 

[yx.yang]

Hi,
My design is working perfectly good after the post-synthesis (using DC) at clock rate of 5 ns.

In place and route(using encounter), I got 50 setup violating path. I tried to simulate the netlist and it worked but with a clock of 40 ns (might be not the corner but it didn't work with 5 ns or even 20 ns).

My question: is it possible to perform optimization here and how effective would that be, would I be able to simulate at 5 ns. Also, how can such optimization be performed?

For "I got 50 setup violating path.", 50 means 50ns or 50ps?
If it's 50ns, you can pass sim at clk period is 40ns is because:
1): You simulation pattern doesn't cover all the cases.
2): Some path with big violation amybe false path or multi-cycle path.
3): Some pattern can never happen in your design, while DC/PT never know that.

If it's 50ps, you must not just setup timing problem but also hold timing problem, cross clock domain problem, ... .

 

[eng.obd_md]

Thanks for the reply, actually 50 is the number of paths violating the setup time. But I am still confused so if they are false paths how come the simulation doesn't work with 5 ns clock.

 

[venky4u]

this is wild guess.. i am not sure of it.

it seems to be you are running the design in functional mode with DC netlist , and if you are running in scan mode in ICC, the frequency used for scan mode operations is different from functional modes and generally it is less.
so this might be causing problem.

 

[ebuddy]

Hi,
My design is working perfectly good after the post-synthesis (using DC) at clock rate of 5 ns.

In place and route(using encounter), I got 50 setup violating path. I tried to simulate the netlist and it worked but with a clock of 40 ns (might be not the corner but it didn't work with 5 ns or even 20 ns).

My question: is it possible to perform optimization here and how effective would that be, would I be able to simulate at 5 ns. Also, how can such optimization be performed?

In your synthesis tool, do the "report timing", and in Encounter, do the report timing again. Find out why timing is worsened by 10 times. What is your standard cell process? I bet is not an issue of optimization. There is something wrong with either your synthesis or your layout.

 

[srideepa]

Hi,
A PnR tool adding a datapath slack of around 35 ns(Without considering clock skew), sounds very fishy. Optimization can be performed using optDesign command in place, clock and route stages. But you have to emphasize that timing is your priority.
Below are some of my questions :
Are you using same constraints in both the tools ?
Do you have the set_propagated_clock true in your postLayout sdc file ?
Are you starting with 65% - 70% utilization ?
Did you check your setup slack at clock stage as well ?
Finally, can you get help for checking your PnR scripts ?

Regards,
R.Srideepa