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# Possible to build a FULL ADDER CIRCUIT using 2-4 decoder...

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#### student2005

##### Member level 3
full adder circuit

Is it possible to build a FULL ADDER circuit using 2-4 decoder & OR gate? Pls advise the approach if it's possible. Many thanks.

#### instruite

##### Advanced Member level 4
full adder decoder

It is possible to build adder using decoders
But full adder has 3 inputs so you should be basically using 3:8 decoder

The logic is simple for full adder there are 2 outputs - Sum and carry
Now use the input of Full adder A B and C (previous carry) as input to the decoder
Depending on the state of inputs the output line will be either 0 or 1
now use a OR gate and OR the lines which have 1 output during the desired state of inputs
apply the same for carry too

momna

### momna

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#### sunking

##### Advanced Member level 3
full adder using decoder

of course you can
all the m*n you can get from 2-4 decoder

#### student2005

##### Member level 3
full adder with decoder

sunking said:
all the m*n you can get from 2-4 decoder
Would u pls advise how to get the logic expressions shown in the figure attached in your last post?

Only ONE 2-4 decoder will do the job?
Thanks

#### sp

##### Full Member level 6
full adder using 3 to 8 decoder

in VHDL

sum <= a xor b xor carry_in; -- each is 1 bit
carry_out <= (a AND b) OR (a AND carry_in) OR (b AND carry_in); -- either 2 of the input is 1 then there is a carry out

we need bout 7 basic logic gates... how many gates required to build the decoder? is it cost effective?

i wonder is it better way to use decoder as multiplier so no complicated algorithm required...

regards,
sp

#### student2005

##### Member level 3
decoder and encoder using full adder

sp said:
... we need bout 7 basic logic gates... how many gates required to build the decoder? is it cost effective?
How many OR gate is required?

#### sp

##### Full Member level 6
full adder using a 3-to-8 decoder

as u can c....

Code:
carry_out <= (a AND b) OR (a AND carry_in) OR (b AND carry_in);

there is 2 OR gates require... but wad's the point asking this question?..

actually the carry_out input part is still able to optimize by boolean algebra... but i lazy to do tht..

regards,
sp

#### student2005

##### Member level 3
obtain a full adder using appropriate decoder

sp said:
as u can c....

Code:
carry_out <= (a AND b) OR (a AND carry_in) OR (b AND carry_in);

there is 2 OR gates require... but wad's the point asking this question?..

actually the carry_out input part is still able to optimize by boolean algebra... but i lazy to do tht..
Say we are allowed to use 2-to-4 decoder IC. Besides OR gates, how many 2-to-4 decoder do you think we need for the circuit mentioned above? Thanks.

#### sp

##### Full Member level 6
3 to 8 decoder full adder

sorry for misleading u... i am using the HDL code n do on CPLD/FPGA...

the hardware generated(synthesis output) is just basic gates.... only OR, AND, XOR gates are use(like in my code).... no decoder required

for ur case...in the output of decoder there are alwasy single '1' and others are '0'...

Code:
input (s1,s2)   output (q3,q2,q1,q0)   adder_output (f)
input 00 =>     output 0001                 0
input 01 =>     output 0010                 1
input 10 =>     output 0100                 1
input 11 =>     output 1000                 0

doing the K-map optimization...q3 to q0 as input & 'f' as output in K-map... i get

f = (q3_not * q1_not * q0_not) + (q1)

using the de morgan law(if i am not mistaken) => change the sign & mend the line

f = NOT(q3 + q1 + q0) + q1

yeah... but u still need a NOT gate... i dunno how to do the NOT gate from OR gate... hehehe...

do urself...

assume ur full adder is without a carry in and carry out.... tht one u hav to do urself as well... i hate K-map

regards,
sp

#### student2005

##### Member level 3
full adder using a decoder

I think ONE 2-to-4 decoder is enough to implement a HALF adder. But I'm not sure whether ONE 2-t0-4 decoder is enough to implement a FULL adder or not. Or, we need TWO 2-to-4 decoders to implement a FULL adder?

Pls advise...

#### sp

##### Full Member level 6
how to implement full adder using decoder

full adder require 3 input; a & b & "carry in"
and 2 output is required; f & "carry out"

so like wad previous guy mention... u need 3-8 decoder and not 2-4 decoder...

anyway...i think again.. it is really interesting in building full adder using the decoder n OR gate...

using this 2 logic.... mayb we can build a NOT gate as well... n solve the inverse part of the boolean equation...

i think 1 decoder is not enuff... if the constraint is use decoder n OR gate only... 2 might b enuff...

regards,
sp

ofogh

### ofogh

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#### student2005

##### Member level 3
full adder using decoder and gates

sunking said:
of course you can
all the m*n you can get from 2-4 decoder
sp, thanks for your explanation. But I just wander why sunking said all the m*n can get from 2-4 decoder. However, he has not mentioned how many of 2-4 decoder is required. Any idea?

ofogh

### ofogh

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#### sp

##### Full Member level 6
build adder

i have no idea wad he meant as well... mayb u can wait for him to reply or u can try to PM him...

i dont understand his equation as well....

regards,
sp

#### timer

##### Junior Member level 3
circuit of 2-4 decoder

It is possible to build a full adder using 2:4 Decoder with an extra Enable input.

You will need 2 2:4 decoders, a NOT gate and 2 4-input OR gates :

This can be done by giving inputs a,b to both the decoders and '~c' as an enable input to the 1st decoder, and 'c' as an enable input to the 2nd decoder. The outputs lines 1,2,4,7 are OR-ed to give the sum, and the output lines 3,5,6,7 are OR-ed to give the carry. (The output lines are numbered from 0 to 3 for the 1st dec and 4 to 7 for the 2nd dec).

If you are not allowed to use a NOT gate, then you would require 3 2:4 decoders, where an extra decoder is used to implement the NOT function.
Hope this helps.

V
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#### student2005

##### Member level 3
boolean equation for full adder

I tried to implement the full adder using TWO 2-4 decoders and THREE 2-input OR gates. The truth tables and the circuit implementation are shown in the attached figure. Pls advise if there is mistake. Many thanks.

V
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