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Don't know that you can reliably predict which circuits may have convergence problems. I've had fairly simple (I thought) circuits that have had convergence problems. A typical source of problems is a circuit that suddenly changes states, such as one with a switch. Non-linear devices can also sometimes generate difficulty.
Very often I have observed convergence problems when performing a TRAN analysis with the ideal opamp model "opamp" (which has inherent hard limiting supply voltages). Hence, it is better to use realistic opamp models.
Many years ago when I tried to implement in PSPICE certain circuits operating at very short switching intervals (in the case, a special type of SMPS operating at well over 500MHz) for some reason the result did not show the expected behavior in the output, even using a circuit taken from an application note.
Although on occasion have failed to solve the problem on simulation, the result became less discrepant after adjusting some configuration parameters of the simulator.
First you ought to say whether you are talking about DC
/ initial conditions convergence, or transient convergence
(timestep errors).
In either case the root cause is numerical behavior and
the difficulty of getting a solution to fit every element.
But what is difficult, or problematic, depends on what you
are trying to do.
For DC solutions you worry about extremely high or low
impedances, anything driven by ideal current sources,
anything with a non-limiting transfer function (like, you
do not want to fit anything with a parabolic function
because it goes crazy further out; a tanh() can be made
to fit nearly the same but with a well known limit beyond
where you might look, but simulator iteration might land
in between first and final guess).
Now many op amp macromodels use the hell out of such
ideal elements, and can be parameterized or driven into
unsolvable operation. You could, by peering into the
error messages enough, deduce where the problems lie
and maybe change the topology or values or expressions
to get a similarly behaving but more solution friendly
result.
For transient timestep problems, it's almost always about
some too-ideal FET model with no capacitance and thus
a node that moves too fast for the declared initial time
step or min time step; solution steps past the point of
no return, cannot back-step to before the edge and will
fail to downrange far enough (because it needed to roll
back, not downrange) and circuit memory "remembers"
something so bogus it can't be solved. Again, macromodels
may do cute things like make a gain node with no C on it,
expecting the assembly to do the frequency response
emulation elsewhere - and maybe this works fine, during
testing, but other conditions produce other outcomes
than proper; the zero-C high gain node must still meet
solution criteria, locally, but likes to blow up (or worse,
has two viable solutions, one convergent, one divergent
later, both equally likely to be picked by interim solution
points in-the-now).
Some settings can relieve somewhat the convergence
difficulty, but often at some cost to accuracy, and the
convergence can be improved sometimes, counterintuitively,
by making convergence criteria -more- demanding than
less; tighter solutions pointwise leave less error residue
and less overshoot (shooting beyond where the models
are fitted, can give you unanticipated behavior). But you
may not like the speed penalty you pay - other than, a
failed run's solution speed means nothing.
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